Datasheet

LTC3626
21
3626f
APPLICATIONS INFORMATION
Although all dissipative elements in the circuit produce
losses, three main sources account for the majority of the
losses in the LTC3626: 1) I
2
R loss, 2) switching losses
and quiescent current loss, 3) transition losses and other
system losses.
1. I
2
R loss is calculated from the DC resistance of the
internal switches, R
SW
, and external inductor, R
L
.
In continuous mode, the average output current will
flow through inductor L but is “chopped” between the
internal top and bottom power MOSFETs. Thus, the
series resistance looking into the SW pin is a function
of both the top and bottom MOSFET’s R
DS(ON)
and the
duty cycle (DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) +(R
DS(ON)BOT
)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus to obtain I
2
R loss:
“I
2
R Loss” = I
OUT
2
• (R
SW
+ R
L
)
2. The internal LDO supplies the power to the INTV
CC
rail.
The total power loss here is the sum of the switching
losses and quiescent current losses from the control
circuitry.
Each time a power MOSFET gate is switched from low
to high to low again, a packet of charge, dQ, moves
from SV
IN
to ground. The resulting dQ/dt is a current
out of INTV
CC
that is typically much larger than the DC
control bias current. In continuous mode, I
GATECHG
=
f(Q
T
+ Q
B
), where Q
T
and Q
B
are the gate charges of the
internal
top and bottom power MOSFETs and f is the
switching frequency. For estimation purposes, (Q
T
+
Q
B
) on the LTC3626 is approximately 2.5nC. To calculate
the total power loss from the LDO load, simply add the
gate charge current and quiescent current and multiply
by SV
IN
:
P
LDO
= (I
GATECHG
+ I
Q
) • V
IN
3. Other “hidden” losses such as transition loss, cop-
per trace resistances, and internal load currents can
account for additional efficiency degradations in the
overall power system. Transition loss arises from the
brief amount of time the top power MOSFET spends in
the saturated region during switch node transitions.
Other losses, including diode conduction losses during
dead time and inductor core losses, generally account for
less than 2% total
additional loss.
Thermal Considerations
The LTC3626 requires the exposed package backplane
metal (PGND) to be well soldered to the PC board to provide
good thermal contact. This gives the QFN package excep-
tional thermal properties, compared to other packages
of similar size, making it difficult in normal operation to
exceed the maximum junction temperature of the part. In
many applications, the LTC3626 does not generate much
heat
due to its high efficiency and low thermal resistance
package backplane. However, in applications in which
the LTC3626 is running at a high ambient temperature,
high input voltage, high switching frequency, and maxi-
mum output current, the generated heat may exceed the
maximum junction temperature of the part. If the junction
temperature reaches approximately 175°C, both power
switches will be turned off until temperature decreases
approximately 10°
C.
Thermal analysis should always be performed by the user
to ensure the LTC3626 does not exceed the maximum
junction temperature.
The temperature rise is given by:
T
RISE
= P
D
• θ
JA
where P
D
is the power dissipated by the regulator and θ
JA
is the thermal resistance from the junction of the die to
the ambient temperature.
Consider the example in which an LTC3626EUDC is operat-
ing with I
OUT
= 2.5A, PV
IN
= SV
IN
= 12V, f = 2MHz, V
OUT
= 1.8V, and an ambient temperature of 70°C. From the
Typical Performance Characteristics section the
R
DS(ON)
of the top switch is found to be nominally 130mΩ while
that of the bottom switch is nominally 85mΩ yielding an
equivalent power MOSFET resistance R
SW
of:
R
DS(ON)TOP
•
1.8
12
+R
DS(ON)BOT
•
10.2
12
=92mW