Datasheet

LTC3625/LTC3625-1
10
3625f
operaTion
converter will turn off. Once V
MID
has again risen above
the V
MID(GOOD)
threshold, the boost converter will be
re-enabled. In the case where V
OUT
< V
MID
, the boost
converter will operate in trickle charge mode until V
OUT
exceeds V
MID
(see Boost Converter).
3. During phase 2, if C
BOT
exceeds its individual maximum
threshold voltage (2.45V/2.05V typical if V
SEL
is low
or 2.7V/2.3V typical if V
SEL
is high) or if V
TOP
exceeds
V
BOT
by more than 50mV (typical), then the appropri-
ate converter will turn off until the capacitor has fallen
below its hysteresis threshold (2.40V/2V typical if V
SEL
is low and 2.65V/2.25V typical if V
SEL
is high for the
buck converter or V
TOP
< V
MID
– 50mV typical for the
boost converter).
4. Once V
OUT
has reached its programmed output voltage,
the part will enter sleep mode, and only minimal power
will be consumed (see the Electrical Characteristics
table).
5. If the supercapacitors’ self discharge or an external load
cause the output to drop by more than 135mV (typical),
then the LTC3625/LTC3625-1 will exit sleep mode and
begin recharging the supercapacitor stack.
In all cases, whenever either of the converters is shut
down, it will switch to its appropriate discharge phase
(NMOS on for the buck and PMOS on for the boost) until
the inductor current reaches 0mA. This optimizes charge
delivery to the output capacitors.
Charge time is dependent on the programmed buck out-
put current as well as the value of supercapacitors being
charged. For estimating charge profiles in the dual inductor
application, see the Typical Performance Characteristics
graph Charge Time vs R
PROG
.
The effective average V
OUT
referred charge current, while
both converters are continuously active, can be approxi-
mated as:
I I A
V
V
CHARGE BUCK BOOST
MID
OUT
≅






0 5 1 1 2. • – • – • •ε
And, while both supercapacitors are in balance and V
MID
is above the V
MID(GOOD)
threshold as:
I
CHARGE
≅ 0.5 • I
BUCK
• ε
BOOST
where ε
BOOST
is the boost converter efficiency which is
typically around 85% (see the Typical Performance Char-
acteristics graph Boost Efficiency vs V
TOP
).
Seen another way this is the maximum steady-state load
the part can support without losing V
OUT
regulation.
PGOOD PIN
The PGOOD pin is an open-drain output used to indicate
that V
OUT
has approached its final regulation value. PGOOD
remains active low until V
OUT
reaches 92.5% of its regula-
tion value at which point it will become high impedance.
If V
OUT
falls below 89.5% of its regulation voltage after
PGOOD has been asserted, PGOOD will once again pull
active low. PGOOD is an open-drain output and requires
a pull-up resistor to the input voltage of the monitoring
microprocessor or another appropriate power source.
PGOOD is pulled active low in shutdown or input UVLO.
Power-Fail Input Comparator
The PFI/PFO pins provide an input failure notification to
the user. The PFI pin is a high impedance input pin that
should be tied to a resistive divider from V
IN
. PFO is an
open-drain output and requires a pull-up resistor to the
input voltage of the monitoring microprocessor or another
appropriate power source. When PFI is above 1.2V, PFO is
high impedance and will be pulled up through the external
resistor. If PFI drops below 1.2V, PFO will be pulled low
indicating a power failure. This allows the user to program
any desired input power failure indication threshold. There
is 15mV of hysteresis on the PFI pin. If this functionality
is not desired the PFI pin should be tied to V
IN
. PFO is
pulled active low in shutdown or input UVLO
Shutdown Operation
When the EN pin is pulled low the LTC3625/LTC3625-1 are
put into shutdown. In this case, all of the active circuitry is
powered down and there will be less than 1µA of leakage
current from both V
IN
and V
OUT
. This allows the input to
be present or absent as well as the capacitor stacks to be
fully charged or discharged in shutdown without leakage
between V
IN
, V
OUT
and GND.