Datasheet

LTC3618
17
3618fc
For more information www.linear.com/LTC3618
Run and Soft-Start
The RUNx pins provide a means to shut down each chan-
nel of
the LTC3618. Pulling both pins below 0.3V places
the
LTC3618 in a low quiescent current shutdown state
(I
Q
< 1µA).
After enabling the LTC3618 by bringing the RUNx pins
above the threshold, the enabled channels enter a soft-
start-up state. The type of soft-start behavior of V
DDQ
is
set by the TRACK/SS1 pin. The soft-start cycle begins with
an initial discharge pulse pulling down the TRACK/SS1
pin to SGND and discharging the external capacitor C
SS
(see Figure 3).
The initial discharge is adequate to discharge capacitors
up to 33nF. If a larger capacitor is required, connect the
external soft-start resistor R
SS
to the RUN pin to fully
discharge the capacitor.
1. Tying this pin to SV
IN
selects the internal soft-start
circuit for V
DDQ
to the final value within 1ms.
2. If a longer soft-start period is desired, it can be
set externally with a resistor and capacitor on the
TRACK/SS1 pin as shown in Figure 3. The voltage ap-
plied at
the TRACK/SS1 pin sets the value of the internal
reference at V
FB1
until TRACK/SS1 is pulled above 0.6V.
The external soft-start duration can be calculated by
using the following equation:
t
SS1
= R
SS
• C
SS
• In
SV
IN
SV
IN
– 0.6V






3. The TRACK/SS1 pin can be used to track the output
voltage of another supply.
The VTTR voltage follows the soft-start behavior of
V
DDQ
at the same rate and ramps up V
TT
output voltage.
If RUN2 is pulled high later than RUN1, VTTR will follow
its internal soft-start, and ramps output voltage of V
TT
at a rate of approximately 850mV/ms.
Regardless of either the internal or external soft-start
state, the MODE/SYNC pin is ignored during start-up and
defaults to
pulse
-skipping mode. In addition, the PGOOD
pin is kept low, and the frequency foldback function is
disabled.
Output Voltage Tracking Input
In the run state, the TRACK/SS1 pin can be used to track
down/up the output voltage of another supply for V
DDQ
. If
V
TRACK/SS1
again drops below 0.6V, the LTC3618 enters
the down-tracking state and V
DDQ
is referenced to the
TRACK/SS1 voltage. If V
TRACK/SS1
reaches 0.1V value
the switching frequency is reduced by 4x to ensure that
the minimum duty cycle limit does not prevent the output
from following TRACK/SS1 pin. The run state will resume
if V
TRACK/SS1
again exceeds 0.6V and V
DDQ
is referenced
to the internal reference.
Efficiency Considerations
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc.
are the individual losses as a percentage of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses: V
IN
quiescent current and I
2
R losses. The V
IN
quiescent current loss dominates the efficiency loss at
very low load currents whereas the I
2
R loss dominates
the efficiency loss at medium to high load currents. In a
typical efficiency plot, the efficiency curve at very low load
currents can be misleading since the actual power lost is
of little consequence.
1. The V
IN
quiescent current is due to two components: the
DC bias current as given in the Electrical Characteristics
and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
from switching the gate capacitance of
the internal power
MOSFET
switches. Each time the gate is switched from
high to low to high again, a packet of charge dQ moves
from V
IN
to ground. The resulting dQ/dt is the current
out of V
IN
due to gate charge, and it is typically larger
than the DC bias current. Both the DC bias and gate
charge losses are proportional to V
IN
, thus, their effects
will be more pronounced at higher supply voltages.
applicaTions inForMaTion