Datasheet

LTC3618
16
3618fc
For more information www.linear.com/LTC3618
Output Voltage Programming
The output voltage of V
DDQ
is set by external resistive
dividers. For example, V
DDQ
can be set according to the
following equation:
V
DDQ
= 0 .6V • 1+
R1
R2
The resistive divider allows pin V
FB1
to sense a fraction
of the output voltage as shown in Figure 3.
Pulse-Skipping Mode
V
DDQ
pulse-skipping mode, which is a compromise
between low output voltage ripple and efficiency, can be
implemented by connecting the MODE/SYNC pin to SV
IN
.
In this condition, the peak inductor current is limited by
the minimum on-time of the current comparator. The low
-
est output voltage ripple is achieved while still operating
discontinuously. During very light output loads, pulse-
skipping allows only a few switching cycles to skip while
maintaining the output voltage in regulation.
Internal and External Compensation
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC load current.
When a load step occurs, like the one shown in Figure 5,
V
OUT
shifts by an amount equal to ∆I
LOAD
• ESR, where
ESR is the effective series resistance of C
OUT
. ∆I
LOAD
also begins to charge or discharge C
OUT
, generating the
feedback error signal that forces the regulator to adapt
to the current change and return V
OUT
to its steady-state
value. During this recovery time, V
OUT
can be monitored
for excessive overshoot or ringing, which would indicate
a stability problem. The availability of the ITH pin allows
the transient response to be optimized over a wide range
of output capacitance.
The ITH1 external components (15.8k and 470pF) shown
in Figure 3 will provide an adequate compensation as
well as a starting point for most applications. The values
can be modified slightly to optimize transient response
once the final PCB layout is complete and the particular
output capacitor type and value have been determined.
The output capacitors need to be selected because the
various types and values determine the loop gain and
phase. The gain of the loop will be increased by increas
-
ing R
C
and the bandwidth of the loop will be increased
by decreasing C
C
. If R
C
is increased by the same factor
that C
C
is decreased, the zero frequency will be kept the
same, thereby keeping the phase shift the same in the
most critical frequency range of the feedback loop. The
output voltage settling behavior is related to the stabil
-
ity of the
closed-loop system. The external compensa-
tion, forced continuous
operation circuit in the Typical
Applications sec
tion uses faster compensation to improve
load step response.
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. More output
capacitance may be required depending on the duty cycle
and load step requirements.
If the ITH pin is tied to SV
IN
, the internal compensation
is selected.
applicaTions inForMaTion
Figure 5. Load Step Transient in FCM with
External Compensation
I
L
1A/DIV
V
OUT
200mV/DIV
3618 F05
V
IN
= 3.3V
V
OUT
= 1.8V
I
LOAD
= 600mA TO 2A
COMPENSATION AND OUTPUT
CAPACITOR VALUES OF FIGURE 3