Datasheet

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LTC3618

3618fc

For more information www.linear.com/LTC3618

Typical applicaTion

DescripTion

Dual 4MHz, ±3A

Synchronous Buck Converter

for DDR Termination

The LTC

3618 is a dual synchronous step-down regulator

using a current mode, constant-frequency architecture. It

provides a complete DDR solution with an input voltage

range from 2.25V to 5.5V.

The output of the first step-down regulator offers a high

accuracy V

DDQ

supply. A buffered reference generates

VTTR at 50% of VDDQIN and drives loads up to ±10mA.

The second regulator generates the DDR termination volt

age (V

) equal to VTTR. Both regulators are capable of

delivering ±3A of load current at 1MHz switching frequency.

The operating frequency is externally programmable up to

4MHz, allowing the use of small surface mount inductors.

0°, 90°, or 180° of phase shift between the two channels

can be selected to minimize input current ripple. For

switching noise-sensitive applications, the LTC3618 can

be synchronized to an external clock up to 4MHz.

The LTC3618 is offered in leadless 24-pin 4mm × 4mm

QFN and thermally enhanced 24-pin TSSOP packages.

Efficiency and Power Loss vs Load Current

FeaTures

applicaTions

DDR Power Supply, Termination and Reference

High Efficiency: Up to 94%

Dual Outputs with ±3A Output Current Capability

2.25V to 5.5V Input Voltage Range

±1% Output Voltage Accuracy

Output Voltage Down to 0.5V

Shutdown Current ≤1µA

VTTR = VDDQIN/2, V

FB2

= VTTR

Adjustable Switching Frequency Up to 4MHz

Internal or External Compensation

Selectable 0°/90°/180° Phase Shift Between Channels

Internal or External Soft-Start for V

DDQ

, Internal

Soft-Start for V

Power Good Status Outputs

Low Profile 4mm × 4mm QFN-24 and TSSOP-24

Packages

DDR Memory

Supports DDR, DDR2, and DDR3 Standards

Tracking Supplies

L, LT , LT C , LT M , Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Protected by U.S. Patents, including 5481178, 6498466, 6580258, 6611131.

LOAD CURRENT (A)

EFFICIENCY (%)

POWER LOSS (W)

0.1

0.01

100

3618 TA01b

0.1 10.01

DDQ

= 1.8V

= 0.9V

SW1

VDDQIN

FB1

LTC3618

3618 TA01a

SGND

PGND

RUN1

TRACK/SS1

ITH1

PHASE

RUN2

PGOOD2

ITH2

PGOOD1

VTTR

MODE/SYNC

3.3V

IN1

IN2

100µF

0.01µF

SW2

FB2

1µH

47µF

0.9V/±3A

1µH

47µF

DDQ

1.8V/3A

422k

210k

392k

REF

DDQ

Summary of content (24 pages)

PAGE 1
LTC3618 Dual 4MHz, ±3A Synchronous Buck Converter for DDR Termination Description Features n n n n n n n n n n n n n n DDR Power Supply, Termination and Reference High Efficiency: Up to 94% Dual Outputs with ±3A Output Current Capability 2.25V to 5.5V Input Voltage Range ±1% Output Voltage Accuracy VTT Output Voltage Down to 0.
PAGE 2
LTC3618 Absolute Maximum Ratings (Notes 1, 10) PVIN1, PVIN2 Voltages................................... –0.3V to 6V SVIN Voltage................................................. –0.3V to 6V SW1 Voltage ..............................–0.3V to (PVIN1 + 0.3V) SW2 Voltage...............................–0.3V to (PVIN2 + 0.3V) RUN1 Voltage............................... –0.3V to (SVIN + 0.6V) All Other Pins................................................ –0.
PAGE 3
LTC3618 Electrical Characteristics The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2), SVIN = PVINx = 3.3V, RT = 178k, unless otherwise specified. SYMBOL PARAMETER VIN Operating Voltage Range VUVLO Undervoltage Lockout Threshold CONDITIONS MIN l SVIN Ramping Down TYP 2.25 5.5 1.8 2.
PAGE 4
LTC3618 Electrical Characteristics The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2), SVIN = PVINx = 3.3V, RT = 178k, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN VMODE (Note 8) VMODE High Voltage Pulse-Skipping Mode 1.
PAGE 5
LTC3618 Typical Performance Characteristics TA = 25°C, VIN = 3.3V, f = 1MHz, Figure 3 Circuit, unless otherwise noted. Efficiency vs Load Current 100 100 VMODE/SYNC = SVIN 90 80 80 70 70 70 60 50 40 30 60 50 40 30 20 VOUT = 2.5V VOUT = 1.8V VOUT = 1.5V 10 0 0.01 0.1 1 LOAD CURRENT (A) EFFICIENCY (%) 80 20 0 0.01 10 3618 G01 50 0 2.25 VOUT Load Regulation 0.8 0.4 80 0.6 0.3 70 0.4 60 0.2 20 10 0 2.25 2.75 3.25 3.75 4.25 4.75 INPUT VOLTAGE (V) 5.25 0.2 VTT = 0.
PAGE 6
LTC3618 Typical Performance Characteristics TA = 25°C, VIN = 3.3V, f = 1MHz, Figure 3 Circuit, unless otherwise noted. Load Step Transient in Forced Continuous Mode, Internal Compensation Load Step Transient in Forced Continuous Mode, Internal Compensation VDDQ 500mV/DIV IL 2A/DIV 10µs/DIV VIN = 5V VDDQ = 1.8V ILOAD = –3A TO 3A VTT 100mV/DIV VTT 100mV/DIV IL 1A/DIV IL 1A/DIV 3618 G10 20µs/DIV VIN = 5V VTT = 0.9V ILOAD = –1A TO 1A Switch On-Resistance vs Input Voltage 0.606 0.604 100 0.
PAGE 7
LTC3618 Typical Performance Characteristics unless otherwise noted. Switch Leakage Current vs Temperature 1.8 No Load Supply Current vs Input Voltage VIN = 5.5V 1.4 1.2 1.0 MAIN SWITCH 0.8 0.6 0.4 0.2 SYNCHRONOUS SWITCH SUPPLY CURRENT (mA) SWITCH LEAKAGE (µA) 1.6 No Load Supply Current vs Temperature 5.0 5.0 4.5 4.5 4.0 4.0 SUPPLY CURRENT (mA) 2.0 TA = 25°C, VIN = 3.3V, f = 1MHz, Figure 3 Circuit, 3.5 3.0 2.5 2.0 1.5 0 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 1.0 2.
PAGE 8
LTC3618 Pin Functions (FE/UF) PHASE (Pin 1/Pin 4): Phase Shift Selection. If pin is tied to SGND, the phase between SW1 and SW2 will be 0°. Tying PHASE to SVIN will select 180° phase shift. With the PHASE pin tied to half of the SVIN voltage, 90° phase shift will be selected. VFB2 (Pin 2/Pin 5): Voltage Feedback Input Pin for VTT. See VFB1. ITH2 (Pin 3/Pin 6): Error Amplifier Compensation of VTT. See ITH1. VDDQIN (Pin 4 /Pin 7): External Reference Input.
PAGE 9
LTC3618 Pin Functions (FE/UF) MODE/SYNC (Pin 24/Pin 3): Mode Selection. 1. Tying the MODE pin to SVIN or SGND enables pulseskipping mode or forced continuous mode respectively for VDDQ only. The default operation mode for VTT is forced continuous mode. The input to the MODE/SYNC pin should be a digital signal. 2. When a clock signal is applied to this pin, the switching frequency synchronizes to this clock signal and forced continuous mode is selected for VDDQ.
PAGE 10
LTC3618 Operation Main Control Loop The LTC3618 is a dual monolithic step-down DC/DC converter featuring current-mode, constant-frequency operation. The regulated output voltage of the second step-down converter is equal to VDDQIN • 0.5. An additional internal amplifier provides a VTTR output equal to VDDQIN • 0.5, which is capable of driving a ±10mA load. During normal operation, the internal top power switch (P-channel MOSFET) of each channel is turned on at the beginning of its clock cycle.
PAGE 11
LTC3618 Operation Pulse-Skipping Mode Operation Slope Compensation and Inductor Peak Current Connecting the MODE/SYNC pin to SVIN enables pulseskipping mode for VDDQ only. As the load current decreases, the peak inductor current will be determined by the voltage on the ITH1 pin until the ITH1 voltage drops below 550mV, corresponding to 0A. At this point switching cycles will be skipped to keep the output voltage in regulation.
PAGE 12
LTC3618 Applications Information Operating Frequency Selection of the operating frequency is a trade-off between efficiency and component size. High frequency operation allows the use of smaller inductor and capacitor values. Lower frequencies improves efficiency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. Tying the RT pin to SVIN sets the default internal operating frequency to 2.25MHz.
PAGE 13
LTC3618 Applications Information VIN LTC3618 SVIN RT VIN fSW 2.25MHz 0.4V RT LTC3618 SVIN RT VIN fSW ∝1/ROSC SGND 1.2V 0.3V TP LTC3618 SVIN MODE/SYNC SGND fSW 1/TP 3618 F04 Figure 4. Setting the Switching Frequency Frequency Synchronization Phase Selection The LTC3618’s internal oscillator can be synchronized to an external frequency by applying a square wave clock signal to the MODE/SYNC pin.
PAGE 14
LTC3618 Applications Information The largest ripple current occurs at the highest VIN. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation: VOUT V L= • 1– OUT fSW • IL(MAX) VIN(MAX) Inductor Core Selection Once the value for L is known, the type of inductor must be selected. Actual core loss is independent of core size for fixed inductor value, but it is very dependent on the inductance selected.
PAGE 15
LTC3618 Applications Information This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT /2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required.
PAGE 16
LTC3618 Applications Information Output Voltage Programming The output voltage of VDDQ is set by external resistive dividers. For example, VDDQ can be set according to the following equation: VDDQ = 0.6V • 1+ R1 R2 The resistive divider allows pin VFB1 to sense a fraction of the output voltage as shown in Figure 3. Pulse-Skipping Mode VDDQ pulse-skipping mode, which is a compromise between low output voltage ripple and efficiency, can be implemented by connecting the MODE/SYNC pin to SVIN.
PAGE 17
LTC3618 Applications Information Run and Soft-Start Output Voltage Tracking Input The RUNx pins provide a means to shut down each channel of the LTC3618. Pulling both pins below 0.3V places the LTC3618 in a low quiescent current shutdown state (IQ < 1µA). In the run state, the TRACK/SS1 pin can be used to track down/up the output voltage of another supply for VDDQ. If VTRACK/SS1 again drops below 0.6V, the LTC3618 enters the down-tracking state and VDDQ is referenced to the TRACK/SS1 voltage.
PAGE 18
LTC3618 Applications Information 2. I2R losses are calculated from the resistances of the internal switches, RSW, and external inductor RL. In continuous mode the average output current flowing through inductor L is “chopped” between the main switch and the synchronous switch.
PAGE 19
LTC3618 Applications Information Next, calculate the inductor values for approximately 1A ripple current at maximum VIN : L1= 1.8V 1.8V • 1– = 0.54µH 2.25MHz • 1A 5.5V 0.9V 0.9V • 1– = 0.33µH L2 = 5.5V 2.25MHz • 1A Using a standard value of 0.45µH inductor for both channels results in maximum ripple currents of: I L1 = 1.8V 1.8V • 1– = 1.2A 2.25MHz • 0.45µH 5.5V I L2 = 0.9V 0.9V • 1– = 0.71A 2.25MHz • 0.45µH 5.
PAGE 20
LTC3618 Typical Applications External Compensation, Forced Continuous Operation, In-Phase Switching, Common PGOOD Output VIN 3.3V 47µF 47µF 1µF SVIN (2×) PVIN1 RUN1 VDDQIN TRACK/SS1 RC1 15.8k 10pF PGOOD1 ITH1 RT 178k (2×) PVIN2 (2×) SW1 0.47µH 10pF LTC3618 FB1 (2×) SW2 0.01µF VDDQ 1.8V/±3A 47µF R2 422k RT CC1 470pF VTTR R1 845k 0.47µH 47µF MODE/SYNC VTT 0.9V/±3A FB2 PHASE RUN2 100k PGOOD2 ITH2 SGND PGOOD RC2 6.
PAGE 21
LTC3618 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. FE Package 24-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1771 Rev B) Exposed Pad Variation AA 7.70 – 7.90* (.303 – .311) 3.25 (.128) 3.25 (.128) 24 23 22 21 20 19 18 17 16 15 14 13 6.60 ±0.10 2.74 (.108) 4.50 ±0.10 6.40 2.74 (.252) (.108) BSC SEE NOTE 4 0.45 ±0.05 1.05 ±0.10 0.65 BSC 1 2 3 4 5 6 7 8 9 10 11 12 RECOMMENDED SOLDER PAD LAYOUT 4.30 – 4.50* (.
PAGE 22
LTC3618 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UF Package UF Package 24-Lead Plastic QFN (4mm × 4mm) 24-Lead Plastic QFN #(4mm × 4mm) (Reference LTC DWG 05-08-1697) (Reference LTC DWG # 05-08-1697 Rev B) 0.70 ±0.05 4.50 ±0.05 2.45 ±0.05 3.10 ±0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 4.00 ±0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD R = 0.115 TYP 0.75 ±0.
PAGE 23
LTC3618 Revision History REV DATE DESCRIPTION A 11/11 Added DDR Power Supply, Termination and Reference to Features PAGE NUMBER 1 Added conditions to ILIMX specification in Electrical Characteristics 3 Removed Note 5 4 B 12/11 Inserted RUN1 Absolute Maximum Ratings 2 C 10/13 Modified Thermal Considerations section. 18 3618fc Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use.
PAGE 24
LTC3618 Typical Application External Compensation, 500kHz Sync 180° Phasing VIN 2.5V~5V 47µF 1µF 47µF (2×) PVIN1 SVIN RUN1 VDDQIN TRACK/SS1 PGOOD1 ITH1 RT 10pF 750k RC1 10k CC1 1000pF (2×) PVIN2 (2×) SW1 2.2µH 10pF LTC3618 FB1 VTTR 0.01µF (2×) SW2 500kHz 47µF R2 562k RT VREF R1 845k VDDQ 1.5V/±3A 2.2µH 47µF ×2 MODE/SYNC PHASE FB2 VTT 0.75V/±3A RUN2 100k PGOOD2 ITH2 SGND PGOOD PGND 10pF 3618 TA03a Efficiency vs Output Current of VDDQ 100 1.8 90 1.6 80 70 1.4 70 1.