Datasheet

LTC3617
15
3617fa
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses: V
IN
quiescent current and I
2
R losses. The V
IN
quiescent current loss dominates the efficiency loss at
very low load currents whereas the I
2
R loss dominates
the efficiency loss at medium to high load currents. In a
typical efficiency plot, the efficiency curve at very low load
currents can be misleading since the actual power lost is
usually of no consequence.
1. The V
IN
quiescent current is due to two components: the
DC bias current as given in the Electrical Characteristics
and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
from switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
low to high to low again, a packet of charge dQ moves
from V
IN
to ground. The resulting dQ/dt is the current
into V
IN
due to gate charge, and it is typically larger than
the DC bias current. Both the DC bias and gate charge
losses are proportional to V
IN
; thus, their effects will
be more pronounced at higher supply voltages.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
, and external inductor, R
L
. In
continuous mode the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R
DS(ON)
and the duty cycle
(DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Character-
istics curves. To obtain I
2
R losses, simply add R
SW
to
R
L
and multiply the result by the square of the average
output current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses generally account for
less than 2% of the total loss.
Thermal Considerations
In most applications, the LTC3617 does not generate much
heat due to its high efficiency.
applications inForMation
However, in high current applications where the LTC3617
is running at high ambient temperature with low supply
voltage and high duty cycles, such as in dropout, the heat
generated may exceed the maximum junction temperature
of the part. If the junction temperature reaches approxi-
mately 160°C, both power switches will be turned off and
the SW node will become high impedance.
To prevent the LTC3617 from exceeding the maximum
junction temperature, some thermal analysis is required.
The temperature rise is given by:
T
RISE
= (P
D
) • (θ
JA
)
where P
D
is the power dissipated by the regulator and θ
JA
is the thermal resistance from the junction of the die to
the ambient temperature. The junction temperature, T
J
,
is given by:
T
J
= T
A
+ T
RISE
where T
A
is the ambient temperature.
As an example, consider the case when the LTC3617 is
used in a DDR application where V
IN
= 3.3V, I
OUT
= 6A,
f = 1MHz, V
OUT
= 1.25V. The equivalent power MOSFET
resistance R
SW
is:
R
SW
=R
DS(ON)
TOP •
V
OUT
V
IN
+R
DS(ON)
BOT • 1–
V
OUT
V
IN






= 35mΩ•
1.25
3.3
+25mΩ• 1–
1.25
3.3






= 28.79mΩ
The V
IN
current during 1MHz with no load is about 22mA,
which includes switching and internal biasing current
loss, transition loss, inductor core loss and other losses
in the application. Therefore, the total power dissipated
by the part is:
P
D
= I
OUT
2
• R
SW
+ V
IN
• I
VIN
(No Load)
= 36A
2
• 28.79mΩ + 3.3V • 22mA = 1.11W
The QFN 3mm × 5mm package junction-to-ambient thermal
resistance, θ
JA
, is around 43°C/W. Therefore, the junction
temperature of the regulator operating in a 25°C ambient
temperature is approximately:
T
J
= 1.11W • 43°C/W + 25°C = 73°C