Datasheet

LTC3616
22
3616fc
For more information www.linear.com/LTC3616
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses: V
IN
quiescent current and I
2
R losses. The V
IN
quiescent current loss dominates the efficiency loss at
very low load currents whereas the I
2
R loss dominates
the efficiency loss at medium to high load currents. In a
typical efficiency plot, the efficiency curve at very low load
currents can be misleading since the actual power lost is
usually of no consequence.
1. The V
IN
quiescent current is due to two components: the
DC bias current as given in the Electrical Characteristics
and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
from switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
low to high to low again, a packet of charge dQ moves
from V
IN
to ground. The resulting dQ/dt is the current
out of V
IN
due to gate charge, and it is typically larger
than the DC bias current. Both the DC bias and gate
charge losses are proportional to V
IN
; thus, their effects
will be more pronounced at higher supply voltages.
2.
I
2
R losses are calculated from the resistances of the
internal switches, R
SW
, and external inductor, R
L
. In
continuous mode the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R
DS(ON)
and the duty cycle
(DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Character-
istics cur
ves. To
obtain I
2
R losses, simply add R
SW
to
R
L
and multiply the result by the square of the average
output current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses generally account for
less than 2% of the total loss.
Thermal Considerations
In most applications, the LTC3616 does not dissipate
much heat due to its high efficiency.
However, in applications where the LTC3616 is running
at high ambient temperature with low supply voltage and
high duty cycles, such as in dropout, the heat dissipated
may exceed the maximum junction temperature of the
p
art.
If
the junction temperature reaches approximately 170°C,
both power switches will be turned off and the SW node
will become high impedance.
To prevent the LTC3616 from exceeding the maximum
junction temperature, some thermal analysis is required.
The temperature rise is given by:
T
RISE
= (P
D
)(θ
JA
)
where P
D
is the power dissipated by the regulator and
θ
JA
is the thermal resistance from the junction of the die
to the ambient temperature. The junction temperature,
T
J
, is given by:
T
J
= T
A
+ T
RISE
where T
A
is the ambient temperature.
As an example, consider the case when the LTC3616 is in
dropout at an input voltage of 3.3V with a load current of
6A at an ambient temperature of 70°C. From the Typical
Performance Characteristics graph of Switch Resistance,
the R
DS(ON)
resistance of the P-channel switch is 0.035Ω.
Therefore, power dissipated by the part is:
P
D
= (I
OUT
)
2
• R
DS(ON)
= 1.26W
For the QFN package, the θ
JA
is 38°C/W.
Therefore, the junction temperature of the regulator op-
erating at 70°C ambient temperature is approximately:
T
J
= 1.26W • 38°C/W + 70°C = 118°C
We can safely assume that the actual junction temperature
will
not exceed the absolute maximum junction tempera-
ture of 125°C.
Note
that for very low input voltage, the junction tempera-
ture will
be higher due to increased switch resistance,
R
DS(ON)
. It is not recommended to use full load current
for high ambient temperature and low input voltage.
To maximize the thermal performance of the LTC3616 the
exposed pad should be soldered to a ground plane. See
the PCB Layout Board Checklist.
applicaTions inForMaTion