Datasheet
LTC3614
4
3614fa
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3614 is tested under pulsed load conditions such that
T
J
≈ T
A
. The LTC3614E is guaranteed to meet specifi cations from
0°C to 85°C junction temperature. Specifi cations over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3614I is guaranteed to meet specifi cations over the full –40°C to 125°C
operating junction temperature. The junction temperature (T
J
) is calculated
from the ambient temperature (T
A
) and power dissipation (P
D
) according
to the formula: T
J
= T
A
+ (P
D
• θ
JA
°C/W), where θ
JA
is the package thermal
impedance. The maximum ambient temperature is determined by specifi c
operating conditions in conjunction with board layout, the rated package
thermal resistance and other environmental factors.
Note 3: This parameter is tested in a feedback loop which servos V
FB
to
the midpoint for the error amplifi er (V
ITH
= 0.75V).
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating junction
temperature range, otherwise specifi cations are at T
A
= 25°C. V
IN
= 3.3V, RT/SYNC = SV
IN
unless otherwise specifi ed (Notes 1, 2, 11).
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
PGOOD Power Good Voltage Windows TRACK/SS = SV
IN
, Entering Window
V
FB
Ramping Up
V
FB
Ramping Down
–3
3
–6
6
%
%
TRACK/SS = SV
IN
, Leaving Window
V
FB
Ramping Up
V
FB
Ramping Down
9
–9
11
–11
%
%
t
PGOOD
Power Good Blanking Time Entering and Leaving Window 70 105 140 µs
R
PGOOD
Power Good Pull-Down On-Resistance 8 17 33
V
RUN
RUN voltage Input High
Input Low
l
l
1
0.4
V
V
Note 4: External compensation on ITH pin.
Note 5: Tying the ITH pin to SV
IN
enables the internal compensation and
AVP mode.
Note 6: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 7: See description of the TRACK/SS pin in the Pin Functions section.
Note 8: In sourcing mode the average output current is fl owing out of the
SW pin. In sinking mode the average output current is fl owing into the SW
Pin.
Note 9: See description of the MODE pin in the Pin Functions section.
Note 10: Guaranteed by correlation and design to wafer level
measurements for QFN packages.
Note 11: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specifi ed maximum operating junction
temperature may impair device reliability.
TYPICAL PERFORMANCE CHARACTERISTICS
V
IN
= 3.3V, RT/SYNC = SV
IN
unless otherwise noted.
Effi ciency vs Load Current
Burst Mode Operation (V
MODE
= 0V)
Effi ciency vs Load Current
Burst Mode Operation (V
MODE
= 0V)
Effi ciency vs Load Current
OUTPUT CURRENT (mA)
30
EFFICIENCY (%)
90
100
20
10
80
50
70
60
40
1 100 1000 10000
3614 G01
0
10
V
IN
= 2.5V
V
IN
= 3.3V
V
IN
= 5V
V
OUT
= 1.8V
OUTPUT CURRENT (mA)
30
EFFICIENCY (%)
90
100
20
10
80
50
70
60
40
1 100 1000 10000
3614 G02
0
10
V
IN
= 2.5V
V
IN
= 3.3V
V
IN
= 5V
V
OUT
= 1.2V
OUTPUT CURRENT (mA)
30
EFFICIENCY (%)
90
100
20
10
80
50
70
60
40
1 100 1000 10000
3614 G03
0
10
Burst Mode OPERATION
PULSE-SKIPPING
FORCED CONTINUOUS
V
OUT
= 1.8V