Datasheet

LTC3614
18
3614fa
The fi rst circuit in the Typical Applications section uses
faster compensation to improve step response.
A second, more severe transient is caused by switching
in loads with large (>1F) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. More output
capacitance may be required depending on the duty cycle
and load step requirements.
AVP Mode
Fast load transient response, limited board space and low
cost are typical requirements of microprocessor power
supplies. A microprocessor will typically exhibit full load
steps with very fast slew rate. The voltage at the micro-
processor must be held to about ±0.1V of nominal in spite
of these load current steps. Since the control loop cannot
respond this fast, the output capacitors must supply the
load current until the control loop can respond.
Normally, several capacitors in parallel are required to
meet microprocessor transient requirements. Capacitor
ESR and ESL primarily determine the amount of droop or
overshoot in the output voltage.
APPLICATIONS INFORMATION
Figure 4. Load Step Transient Forced
Continuous Mode with AVP Mode
Consider the LTC3614 without AVP with a bank of tantalum
output capacitors. If a load step with very fast slew rate
occurs, the voltage excursion will be seen in both direc-
tions, for full load to minimum load transient and for the
minimum load to full load transient.
If the ITH pin is tied to SV
IN
, the active voltage positioning
(AVP) mode and internal compensation are selected.
AVP mode intentionally compromises load regulation by
reducing the gain of the feedback circuit, resulting in an
output voltage that slightly varies with load current. When
the load current suddenly increases, the output voltage
starts from a level slightly higher than nominal so the output
voltage can droop more and stay within the specifi ed volt-
age range. When the load current suddenly decreases the
output voltage starts at a level lower than nominal so the
output voltage can have more overshoot and stay within
the specifi ed voltage range (see Figures 3 and 4).
The benefi t is a lower peak-to-peak output voltage deviation
for a given load step without having to increase the output
fi lter capacitance. Alternatively, the output voltage fi lter ca-
pacitance can be reduced while maintaining the same peak
to peak transient response. Due to the reduced loop gain
in AVP mode, no external compensation is required.
Figure 3. Load Step Transient Forced
Continuous Mode (AVP Inactive)
V
OUT
200mV/DIV
I
L
1A/DIV
50µs/DIV
3614 F03
V
IN
= 3.3V
V
OUT
= 1.8V
I
LOAD
= 100mA TO 3A
V
MODE
= 1.5V
COMPENSATION FIGURE 1
V
OUT
100mV/DIV
I
L
1A/DIV
50µs/DIV
3614 F04
V
IN
= 3.3V
V
OUT
= 1.8V
I
LOAD
= 100mA TO 3A
V
MODE
= 1.5V
V
ITH
= 3.3V
OUTPUT CAPACITOR VALUE FIGURE 1