Datasheet

LTC3613
27
3613fa
APPLICATIONS INFORMATION
The resulting maximum ripple current is:
ΔI
L
=
1.2V
350kHz•0.56µH
• 1–
1.2V
24V
⎛
⎝
⎜
⎞
⎠
⎟
≈5.8A
Often in high power applications, DCR current sensing is
preferred over R
SENSE
in order to maximize efficiency. In
order to determine the DCR filter values, first the induc-
tor manufacturer has to be chosen. For this design, the
Vishay IHLP-4040DZ-01 model is chosen with a value of
0.56H and DCR
MAX
=1.8m. This implies that:
V
SENSE(MAX)
= DCR
MAX
at 25°C • [1 + 0.4% (T
L(MAX)
– 25°C)] • [I
OUT(MAX)
– ΔI
L
/2]
= 1.8m • [1 + 0.4% (100°C – 25°C)] •
[15A – 5.8A/2]
≈ 28.3mV
The maximum sense voltage is within the range that
LTC3613 can handle without any additional scaling. There-
fore, the DCR filter consists of a simple RC filter across
the inductor. If the C is chosen to be 0.1µF, then the R can
be calculated as:
R
DCR
=
L
DCR
MAX
•C
DCR
=
0.56µH
1.8mΩ•0.1µF
≈3.11k
The closest standard value is 3.09k.
The resulting value of V
RNG
with a 50% design margin
factor is:
V
RNG
= V
SENSE(MAX)
/0.05 • MF
= 28.3mV/0.05 • 1.5 ≈ 850mV
To generate the V
RNG
voltage, connect a resistive divider
from INTV
CC
to SGND with R
DIV1
= 52.3k and R
DIV2
= 10k.
Select C
IN
to give an RMS current rating greater than 7A
at 75°C. The output capacitor C
OUT
is chosen for a low
ESR of 4.5m to minimize output voltage changes due to
inductor ripple current and load steps. The output voltage
ripple is given as:
ΔV
OUT(RIPPLE)
= ΔI
L(MAX)
• ESR = (5.8A)(4.5m)
≈ 26mV
However, a 0A to 10A load step will cause an output
change of up to:
ΔV
OUT(STEP)
= ΔI
LOAD
• ESR = (10A)(4.5m) = 45mV
Optional 100F ceramic output capacitors are included to
minimize the effect of ESR and ESL in the output ripple
and to improve load step response.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3613.
• Multilayer boards with dedicated ground layers are
preferable for reduced noise and for heat sinking pur-
poses. Use wide rails and/or entire planes for V
IN
, V
OUT
and PGND nodes for good filtering and minimal copper
loss. Flood unused areas of all layers with copper for
better heat sinking.
• Keep signal and power grounds separate except at the
point where they are shorted together. Short signal and
power ground together only at a single point with a nar-
row PCB trace (or single via in a multilayer board). All
power train components should be referenced to power
ground and all small-signal components (e.g., C
ITH1
,
R
T
, C
SS
etc.) should be referenced to signal ground.
• Place C
IN
, inductor, sense resistor (if used), and primary
C
OUT
capacitors close together in one compact area.
The SW node should be compact but be large enough
to handle the inductor currents without large copper
losses. Connect PV
IN
as close as possible to the (+)
plate of C
IN
capacitor(s) that provides the bulk of the
AC current (these are normally the ceramic capaci-
tors), and connect PGND as close as possible to the
(–) terminal of the same C
IN
capacitor(s). The high dI/
dt loop formed by C
IN
, the top MOSFET, and the bot-
tom MOSFET should have short leads and PCB trace
lengths to minimize high frequency EMI and voltage
stress from inductive ringing. The (–) terminal of the
primary C
OUT
capacitor(s) which filter the bulk of the
inductor ripple current (these are normally the ceramic
capacitors) should also be connected close to the (–)
terminal of C
IN
.