Datasheet

LTC3610
16
3610ff
applications inForMation
4. C
IN
loss. The input capacitor has the difficult job of filtering
the large RMS input current to the regulator. It must have
a very low ESR to minimize the AC I
2
R loss and sufficient
capacitance to prevent the RMS current from causing
additional upstream losses in fuses or batteries.
Other losses, including C
OUT
ESR loss, Schottky diode D1
conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss.
When making adjustments to improve efficiency, the input
current is the best indicator of changes in efficiency. If you
make a change and the input current decreases, then the
efficiency has increased. If there is no change in input
current, then there is no change in efficiency.
Checking
Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to ΔI
LOAD
(ESR), where ESR is the effective series
resistance of C
OUT
. ΔI
LOAD
also begins to charge or dis-
charge C
OUT
generating a feedback error signal used by the
regulator to return V
OUT
to its steady-state value. During
this recovery time, V
OUT
can be monitored for overshoot
or ringing that would indicate a stability problem. The I
TH
pin external components shown in Figure 6 will provide
adequate compensation for most applications. For a
detailed explanation of switching control loop theory see
Application Note 76.
Design
Example
As a design example, take a supply with the following
specifications: V
IN
= 5V to 24V (12V nominal), V
OUT
=
2.5V ±5%, I
OUT(MAX)
= 12A, f = 550kHz. First, calculate
the timing resistor with V
ON
= V
OUT
:
R
kHz pF
k
ON
=
( )( )
=
1
550 10
182
and choose the inductor for about 40% ripple current at
the maximum V
IN
:
L =
2.5V
550kHz
( )
0.4
( )
12A
( )
1−
2.5V
28V
⎛
⎝
⎜
⎞
⎠
⎟
= 0.86µH
Selecting a standard value of 0.82µH results in a maximum
ripple current of:
ΔI
L
=
2.5V
550kHz
( )
0.82µH
( )
1 –
2.5V
12V
⎛
⎝
⎜
⎞
⎠
⎟
= 4.4A
Next, set up V
RNG
voltage and check the I
LIMIT
. Tying V
RNG
to 0.5V will set the typical current limit to 16A, and tying
V
RNG
to GND will result in a typical current around 19A.
C
IN
is chosen for an RMS current rating of about 5A at
85°C. The output capacitors are chosen for a low ESR
of 0.013Ω to minimize output voltage changes due to
inductor ripple current and load steps. The ripple voltage
will be only:
ΔV
OUT(RIPPLE)
= ΔI
L(MAX)
(ESR)
= (4.4A) (0.013Ω) = 57mV
However, a 0A to 10A load step will cause an output
change of up to:
ΔV
OUT(STEP)
= ΔI
LOAD
(ESR) = (10A) (0.013Ω) = 130mV
An optional 22µF ceramic output capacitor is included
to minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 6.
How to Reduce SW Ringing
As with any switching regulator, there will be voltage ring-
ing on the SW node, especially for high input voltages.
The ringing amplitude and duration is dependent on the
switching speed (gate drive), layout (parasitic inductance)
and MOSFET output capacitance. This ringing contributes
to the overall EMI, noise and high frequency ripple. One
way to reduce ringing is to optimize layout. A good layout
minimizes parasitic inductance. Adding RC snubbers from
SW to GND is also an effective way to reduce ringing. Finally,
adding a resistor in series with the BOOST pin will slow
down the MOSFET turn-on slew rate to dampen ringing,
but at the cost of reduced efficiency. Note that since the
IC is buffered from the high frequency transients by PCB
and bondwire inductances, the ringing by itself is normally
not a concern for controller reliability.