Datasheet

LTC3609
18
3609fb
applicaTions inForMaTion
Figure 6. Design Example: 5V to 32V Input to 2.5V/6A at 550kHz
V
OUT
2.5V AT
6A
GND
V
IN
V
IN
5V TO 32V
C
OUT1
100µF
x2
L1
1.2µH
C
IN
4.7µF
50V
x2
+
LTC3609
SGND
26
NC
25
NC
24
V
FB
23
I
ON
22
NC
21
SGND
20
FCB
19
I
TH
18
V
RNG
17
PGOOD
16
SGND
15
SGND
GND
V
OUT
PV
IN
1
PV
IN
2
PV
IN
3
PV
IN
4
PV
IN
5
PV
IN
6
PV
IN
7
SW
SW
SW
SW
8
NC
9
SGND
10
BOOST
11
RUN/SS
12
V
ON
13
SGND
14
PGND
40
PGND
39
PGND
38
PGND
37
PGND
36
PGND
35
PGND
34
SW
33
INTV
CC
INTV
CC
INTV
CC
32
INTV
CC
PGOOD
31
SV
IN
V
IN
30
EXTV
CC
29
NC
28
SGND
27
SW
41
SW
42
SW
43
SW
44
SW
45
SW
46
SW
47
PV
IN
48
PV
IN
49
PV
IN
50
PV
IN
51
PV
IN
52
3609 F06
C
F
0.1µF
50V
R
F1
1Ω
C
VCC
4.7µF
6.3V
EXTV
CC
C4
0.01µF
INTV
CC
INTV
CC
JP1
C
B1
0.22µF
D
B
CMDSH-3
C
SS
0.1µF
V
IN
C
VON
0.1µF
R1
9.53k
1%
R
PG1
100k
R
ON
187k
1%
R2
30.1k
1%
R5
15.8k
C
C1
1000pF
C
C2
100pF
V
OUT
C
IN
: MURATA GRM32ER71H475K
C
OUT
: MURATA GRM435R60J107M
L
I
: CDEP851R2MC-50
KEEP POWER GROUND AND SIGNAL
GROUND SEPARATE. CONNECT AT
ONE POINT.
2Ω
Design Example
As a design example, take a supply with the following
specifications: V
IN
= 5V to 32V (12V nominal), V
OUT
=
2.5V ± 5%, I
OUT(MAX)
= 6A, f = 550kHz. First, calculate the
timing resistor with V
ON
= V
OUT
:
R
V
V kHz pF
k
ON
=
( )( )( )
=
2 5
2 4 550 10
187
.
.
and choose the inductor for about 40% ripple current at
the maximum V
IN
:
L =
2.5V
550kHz
( )
0.4
( )
6A
( )
1−
2.5V
32V






=1.8µH
Selecting a standard value of 1.5µH results in a maximum
ripple current of:
ΔI
L
=
2.5V
550kHz
( )
1.5µH
( )
1 –
2.5V
12V






= 2.4A
Next, set up V
RNG
voltage and check the I
LIMIT
. Tying V
RNG
to GND will set the typical current limit to 9A, and tying
V
RNG
to 1.2V will result in a typical current around 14A.
C
IN
is chosen for an RMS current rating of about 5A at
85°C. The ceramic output capacitors are chosen for an
ESR of 0.002Ω to minimize output voltage changes due
to inductor ripple current and load steps. The ripple volt-
age is:
∆V
OUT(RIPPLE)
= ∆I
L(MAX)
(ESR)
= (2.4A) (0.002Ω) = 4.8mV
and a 0A to 6A load step will only cause an output
change of:
∆V
OUT(STEP)
= ∆I
LOAD
(ESR) = (6A) (0.002Ω) = 12mV
An optional 22µF ceramic output capacitor is included
to minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 6.