Datasheet

LTC3605A
10
3605afg
For more information www.linear.com/LTC3605A
Multiphase Operation
For output loads that demand more than 5A of current,
multiple LTC3605As can be cascaded to run out of phase
to provide more output current. The CLKIN pin allows the
LTC3605A to synchronize to an external clock (±30% of
frequency programmed by RT) and the internal phase-
locked-loop allows the LTC3605A to lock onto CLKIN’s
phase as well. The CLKOUT signal can be connected to the
CLKIN pin of the following LTC3605A stage to line up both
the frequency and the phase of the entire system. Tying
the PHMODE pin to INTV
CC
, SGND or INTV
CC
/2 generates
a phase difference (between CLKIN and CLKOUT) of 180
degrees, 120 degrees, or 90 degrees respectively, which
corresponds to 2-phase, 3-phase or 4-phase operation. A
total of 12 phases can be cascaded to run simultaneously
out of phase with respect to each other by programming
the PHMODE pin of each LTC3605A to different levels.
Internal/External ITH Compensation
During single phase operation, the user can simplify the
loop compensation by tying the I
TH
pin to INTV
CC
to en-
able internal compensation. This connects an internal 30k
resistor in series with a 40
pF capacitor to the output of
the error amplifier (internal ITH compensation point) while
also activating output voltage positioning such that the
output voltage will be 1.5% above regulation at no load and
1.5% below regulation at full load. This is a trade-off for
simplicity instead of OPTI-LOOP
®
optimization, where ITH
components are external and are selected to optimize the
loop transient response with minimum output capacitance.
Minimum Off-Time and Minimum On-Time
Considerations
The minimum off-time, t
OFF(MIN)
, is the smallest amount of
time that the LTC3605A is capable of turning on the bot-
tom power MOSFET, tripping the current comparator and
turning the power MOSFET back off
.
This time is generally
about 70ns. The minimum off-time limit imposes a maxi
-
mum duty cycle of t
ON
/(t
ON
+ t
OFF(MIN)
). If the maximum
duty cycle is reached, due to a dropping input voltage for
example, then the output will drop out of regulation. The
minimum input voltage to avoid dropout is:
V
IN(MIN)
= V
OUT
•
t
ON
+ t
OFF(MIN)
t
ON
Conversely, the minimum on-time is the smallest dura-
tion of time in which the top power MOSFET can be in
its “on”
state. This time is typically 40ns. In continuous
mode operation, the minimum on-time limit imposes a
minimum duty cycle of:
DC
MIN
= f • t
ON(MIN)
where t
ON(MIN)
is the minimum on-time. As the equation
shows, reducing the operating frequency will alleviate the
minimum duty cycle constraint.
In the rare cases where the minimum duty cycle is sur
-
passed, the output voltage will still remain in regulation, but
the switching frequency will decrease from its programmed
value. This is an acceptable result in many applications, so
this constraint may not be of critical importance in most
cases. High switching frequencies may be used in the
design without any fear of severe consequences. As the
sections on inductor and capacitor selection show, high
switching frequencies allow the use of smaller board com
-
ponents, thus reducing the size of the application circuit.
C
IN
and C
OUT
Selection
The input capacitance, C
IN
, is needed to filter the trapezoi-
dal wave current at the drain of the top power MOSFET.
To prevent large voltage transients from occurring
, a low
ESR input capacitor sized for the maximum R
MS
current
should be used. The maximum R
MS
current is given by:
I
RMS
≅I
OUT(MAX)
V
OUT
V
IN
V
IN
V
OUT
–
1
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
≅ I
OUT
/2. This simple worst-case condition is com-
monly used for design because even significant deviations
do not offer much relief.
Note that ripple current ratings
from capacitor manufacturers are often based on only
2000 hours of life which makes it advisable to further
operaTion
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