Datasheet

LTC3601
17
3601fb
From the previous section, I
GATECHG
is ~4mA when f =
4MHz, and the spec table lists the typical I
Q
to be 1mA.
Therefore, the total power dissipation due to resistive
losses and LDO losses is:
P
D
= I
OUT
2
• R
SW
+ V
IN
• (I
GATECHG +
I
Q
)
P
D
= (1.5)
2
• (0.105) + 12V • 5mA = 296mW
The QFN 3mm × 3mm package junction-to-ambient thermal
resistance, θ
JA
, is around 45°C/W. Therefore, the junction
temperature of the regulator operating in a 70°C ambient
temperature is approximately:
T
J
= 0.296 • 45 + 70 = 83.3°C
which is well below the specifi ed maximum junction
temperature of 125°C.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3601.
1. Do the capacitors C
IN
connect to V
IN
and PGND as close
to the pins as possible? These capacitors provide the AC
current to the internal power MOSFETs and drivers. The
(–) plate of C
IN
should be closely connected to PGND
and the (–) plate of C
OUT
.
2. The output capacitor, C
OUT
, and inductor L1 should
be closely connected to minimize loss. The (–) plate
of C
OUT
should be closely connected to PGND and the
(–) plate of C
IN
.
3. The resistive divider, R1 and R2, must be connected
between the (+) plate of C
OUT
and a ground line termi-
nated near SGND. The feedback signal, V
FB
, should be
routed away from noisy components and traces such as
the SW line, and its trace length should be minimized.
In addition, RT and the loop compensation components
should be terminated to SGND.
4. Keep sensitive components away from the SW pin. The
R
RT
resistor, the feedback resistors, the compensation
components, and the INTV
CC
bypass capacitor should
all be routed away from the SW trace and the inductor.
5. A ground plane is preferred, but if not available the
signal and power grounds should be segregated with
both connecting to a common, low noise reference
point. The point at which the ground terminals of the
V
IN
and V
OUT
bypass capacitors are connected makes a
good, low noise reference point. The connection to the
PGND pin should be made with a minimal resistance
trace from the reference point.
6. Flood all unused areas on all layers with copper in order
to reduce the temperature rise of power components.
These copper areas should be connected to the exposed
backside connection of the IC.
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