Datasheet

LTC3589/LTC3589-1/
LTC3589-2
43
3589ff
For more information www.linear.com/3589
operaTion
The power dissipated by an LDO regulator is estimated by:
P
D(LDOX)
= (V
IN(LDOX)
– V
LDOX
)• I
LDOX
Where V
LDOX
is the programmed output voltage, V
IN(LDOX)
is the LDO supply voltage, and I
LDOX
is the output load
current. If one of the switching regulator outputs is used
as an LDO supply voltage, remember to include the LDO
supply current in the switching regulator load current for
calculating power loss.
An example using the equations above with the parameters
in Table 19 shows an application that is at the maximum
junction temperature of 125°C at an ambient temperature
of 85°C. LDO2, LDO3, and LDO4 are powered by step-
down switching regulator 2 and the buck-boost switching
regulator. The total load on those two switching regula-
tors is the sum of the application load and the LDO load.
This example is with the LDO regulators at one half rated
current and the switching regulators at three quarters
rated current.
Table 19. T
J
Calculation Example
OUTPUT V
IN
V
OUT
APP LOAD TOTAL
LOAD
EFF POWER
DISS
LDO1_VSTB 3.8V 1.2V 10mA 10mA 30mW
LDO2 1.8V 1.2V 100mA 100mA 60mW
LDO3 3.3V 1.8V 100mA 100mA 150mW
LDO4 3.3V 2.5V 100mA 100mA 80mW
V
OUT1
3.8V 1.2V 1.2A 1.2A 80% 290mW
V
OUT2
3.8V 1.8V 0.65A 0.75A 90% 140mW
V
OUT3
3.8V 1.25V 0.75A 0.75A 85% 140mW
V
OUT4
3.8V 3.3V 0.70A 0.90A 90% 300mW
TOTAL POWER 1180mW
INTERNAL JUNCTION TEMPERATURE AT 85°C AMBIENT 125°C
Printed Circuit Board Layout
When laying out the printed circuit board, the following
checklist should be followed to ensure proper operation
of the LTC3589:
1. Connect the exposed pad of the package (Pin 41)
directly to a large ground plane to minimize thermal
and electrical impedance.
2. The switching regulator input supply traces and their
decoupling capacitors should be as short as possible.
Connect the GND side of the capacitors directly to the
ground plane of the board. The decoupling capacitors
provide the AC current to the internal power MOSFETs
and their drivers. It is important to minimize inductance
from the capacitors to the LTC3589 pins.
3. Minimize the switching power traces connecting SW1,
SW2, SW3, and buck-boost switch pins SW4AB and
SW4CD to the inductors to reduce radiated EMI and
parasitic coupling. Keep sensitive nodes such as the
feedback pins away from or shielded from the large
voltage swings on the switching nodes.
4. Minimize the length of the connection between the
step-down switching regulator inductors and the output
capacitors. Connect the GND side of the output capaci-
tors directly to the thermal ground plane of the board.
5. Minimize the length of the connection between the
buck-boost regulator output (BB_OUT) and the output
capacitor. Connect the GND side of the output capacitor
directly to the thermal ground plane of the board.