Datasheet
LTC3589/LTC3589-1/
LTC3589-2
35
3589ff
For more information www.linear.com/3589
Figure 17. IRQ and IRQSTAT Status Register Fault Timing
IRQ
IRQSTAT
CLIRQ
3589 F17
TSD, UV,
OR PGOOD FAULT
1 SEC 1 SEC
Figure 19. LTC3589 I
2
C Serial Port Multiple Write Pattern
1 2 3 4 5 6 7 8 9
0 1 1 0 1 0 0 WR S7 S6 S5 S4 S3 S2 S1 S0 D7 D6 D5 D4 D3 D2 D1 D0 S7 S6 S5 S4 S3 S2 S1 S0 D7 D6 D5 D4 D3 D2 D1 D0
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL
ADDRESS SUB ADDRESS
DATA SUB ADDRESS DATA
3589 F19
ACK
ACK ACK ACK ACK
0
1 1 0 0 0 0
1
START
SDA
STOP
Figure 18. LTC3589 I
2
C Timing
t
SU, DAT
t
HD, STA
t
HD, DAT
SDA
SCL
t
HD, STA
t
HD, STA
t
SU, STO
3589 F18
t
BUF
t
LOW
t
HIGH
START
CONDITION
REPEATED START
CONDITION
STOP START
t
r
t
f
t
SP
operaTion
Figure 17 shows the timing of the IRQ pin and IRQSTAT
status register following a fault induced hard shutdown
event. When a fault occurs, IRQ is latched LOW and bit
IRQSTAT[3], IRQSTAT[5], or IRQSTAT[7] is set. IRQ re-
mains LOW until the CLIRQ command is issued. When the
CLIRQ command has been issued, the IRQSTAT status bit
remains set for the one second enable inhibit time or as
long as the fault condition persists, whichever is longer.
Fault Induced Shutdown
Any of the three fault conditions will initiate a hard reset
shutdown triggering the following events: 1) A bit corre-
sponding to the fault is set in status register IRQSTAT, 2)
IRQ and WAKE pins are pulled LOW, 3) enable pin inputs
are ignored and the regulators are disabled, 4) all enable
bits and software control mode bit in the output voltage
enable OVEN command register are cleared, and 5) the
pushbutton controller is sent to the PDN state for one
second and then to POFF. Re-enabling of regulators is
inhibited until both the fault condition and the one second
time out have passed to allow regulator outputs sufficient
time to discharge. When one second timeout and the fault
condition are both passed, if PWR_ON is HIGH, WAKE will
come up and the LTC3589 will respond to any enable pins
that are also HIGH.