Datasheet

LTC3589/LTC3589-1/
LTC3589-2
34
3589ff
For more information www.linear.com/3589
operaTion
Figure 16. IRQ and IRQSTAT Status Register Warning Timing
IRQ
IRQSTAT
CLIRQ
3589 F16
TSD OR UV
WARNING
If any enabled regulator output falls more than 7% low
for longer than 25µs PGOOD is pulled LOW and a cor-
responding status bit in the PGSTAT register is set to 0.
The PGOOD pin and PGSTAT status bit remain LOW for
as long as the low voltage condition persists plus 250µs.
An extended low output rail causing the PGOOD pin to
be LOW for longer than 14ms defines a PGOOD timeout
fault condition that triggers a hard reset if not masked in
I
2
C register bit SCR2[7]. When SCR2[7] is HIGH, PGOOD
remains in normal operation.
During a dynamic voltage slew, PGOOD is pulled LOW
unless bit 5 in the dynamic target voltage register for
each regulator is set HIGH. The status register PGSTAT
is unaffected by a dynamic voltage slew.
Undervoltage Detection
The LTC3589 undervoltage (UV) detection circuit will out-
put a fault condition, locking out regulator operation, until
V
IN
reaches 2.7V. Once V
IN
is above 2.7V the LTC3589 will
operate normally until V
IN
drops to 2.55V (typical). When
V
IN
drops below 2.55V, the fault condition initiates a hard
shutdown reset. Figure 15 shows undervoltage warning
and fault detection levels.
Thermal Shutdown Fault and Warning
Similar to the V
IN
undervoltage detection circuits the over-
temperature detection circuits check for warning and fault
levels. An overtemperature fault will initiate a fault induced
shutdown. An overtemperature warning sets register bit
IRQSTAT[6] and pulls the IRQ pin LOW.
IRQ Pin and IRQSTAT Status Register Function
The IRQ pin and IRQSTAT status register report PGOOD
timeout fault, V
IN
undervoltage warning and fault, and
high temperature warning and fault. Table 16 shows the
meaning of the IRQSTAT read-only status register bits.
Table 16. IRQSTAT Read-Only Register Bit Definitions
IRQSTAT[BIT] VALUE SETTING
3 1
PGOOD Timeout Fault (PGOOD Low >
14ms)
4 1
V
IN
Undervoltage Warning (V
IN
< 2.9V)
5 1
V
IN
Undervoltage Fault (V
IN
< 2.6V)
6 1
Thermal Limit Warning (T
J
> 130°C)
7 1
Thermal Limit Fault (T
J
> 150°C)
Figure 16 shows the timing of the IRQ and IRQSTAT status
register following a warning (V
IN
<2.9V or high temperature
warning) event. When a warning occurs, IRQ is latched
LOW and bit IRQSTAT[4] or IRQSTAT[5] is set. IRQ remains
low and the IRQSTAT status bits remain active until the
I
2
C CLIRQ command is given and the warning condition
has passed.
Figure 15. UV Detection Hard Reset and Warning Levels
V
IN
UNDERVOLTAGE
V
IN
FAULT
WARNING
3589 F15
2.55V 2.65V 2.9V 3V
An undervoltage warning sets register bit IRQSTAT[4] and
pulls the IRQ pin LOW.
To minimize standby quiescent current the UVLO and
thermal sensor circuits are disabled when all the regula-
tors are off.