Datasheet

LTC3589/LTC3589-1/
LTC3589-2
32
3589ff
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operaTion
Figure 12 shows the start-up timing for the application shown
in Figure 11. There is a 200µs (typical) delay between the
enable pin and the internal enable signal to each regulator.
less of the status of PWR_ON and WAKE. Writing a 1 to
a regulator’s keep-alive bit in its dynamic target voltage
register will keep a regulator alive when the LTC3589 is
in standby (POFF) mode. A regulator with its keep-alive
bit set will stay enabled until the bit is reset writing the bit
LOW, resetting the LTC3589 with a pushbutton hard reset,
or a fault condition (UVLO, PGOOD, timeout or thermal
shutdown) occurs. PGOOD and fault status are reported
in the IRQSTAT and PGSTAT registers and on the IRQ and
PGOOD pins for keep-alive regulators when PWR_ON and
WAKE are LOW.
Software Control Mode
Once a power-up sequence is completed each regulator
may be enabled and disabled individually by the system
as needed for power mode requirements. Setting the out-
put voltage enable command register bit OVEN[7] HIGH
disconnects each regulator from its enable pin so control
is solely through the OVEN command register. To enter
software control mode, set command bit OVEN[7] HIGH
and the desired enable bits in OVEN[6:0] HIGH. Any of the
regulators enabled in OVEN[6:0] will stay on regardless of
the state of their enable pins when OVEN[7] is HIGH. Set-
ting the regulator enable bits and the software control bit in
OVEN[7] may occur on the same I
2
C start-stop sequence. A
normal shutdown using PWR_ON resets all eight bits of the
OVEN register to 0x00 to ensure all regulators are shut off.
FAULT DETECTION, SHUTDOWN, AND REPORTING
The LTC3589 monitors V
IN
, output rail voltages and internal
die temperature. A warning condition is indicated when
V
IN
is less than 2.9V and when internal die temperature
approaches the thermal shutdown temperature. A fault
condition occurs when V
IN
is less than 2.6V, any regulator
output is 8% low for 14ms, or the internal die temperature
is HIGH. Warning and fault states are reported via the IRQ,
PGOOD, and RTSO pins. Specific fault states are read via
the I
2
C serial port status registers IRQSTAT and PGSTAT.
To help ensure startup sequencing, the LTC3589 is de-
signed to block the internal enable of a regulator until its
output has discharged to less than 300mV. The I
2
C system
control register 2 (SCR2) controls whether the LTC3589
waits or enables immediately. The POR default setting for
the LTC3589 and LTC3589-1 is to wait for the output to be
less than 300mV before enabling. The output discharge
resistors on the LTC3589 and LTC3589-1 regulators are
tied to the settings in SCR2.
For use in systems that might back drive the regulator
outputs higher than 300mV, the LTC3589-2 POR default
setting is to always enable regardless of output voltage
and to always engage the discharge resistors whenever
the regulator is not enabled.
Keep-Alive Operation
For systems which require an active supply rail when in
system standby, any of the three LTC3589 step-down
switching regulators or LDO2 may be kept alive regard-
V1
V3
V2
V4
LDO2
LDO3
LDO4
3589 F12
WAKE
1.8V
2.8V
1.2V
3.3V
0.5V
0.5V
1.8V
1V
1.2V
200µs
200µs
200µs
Figure 12. Pin-Strap Sequencing Timing