Datasheet

LTC3589/LTC3589-1/
LTC3589-2
31
3589ff
For more information www.linear.com/3589
Figure 11. Pin-Strap Start-Up Sequence Application Circuit
ON(PB)
PBSTAT
FAULT
WAKE
PWR_ON
CLIRQ
IRQ
3589 F10
µC/µP CONTROL
<1 SEC
Figure 10. Hard Reset Due to a Fault Condition
operaTion
Figure 6. Power-Up Using the Pushbutton
PBSTAT
WAKE
PWR_ON
3589 F06
ON(PB)
µC/µP CONTROL
400ms
<5 SEC
Figure 9. Hard Reset Using the Pushbutton
PBSTAT
WAKE
PWR_ON
RSTO
3589 F09
ON(PB)
µC/µP CONTROL
50ms
1 SEC
5 SEC
Figure 7. Power Down Using Pushbutton
Figure 8. Power-Up and Down Using PWR_ON Pin
3589 F11
EN1
EN2
EN3
EN4
EN_LDO2
EN_LDO34
ON
PWR_ON
LTC3589
PWR_ON
WAKE
SW1
SW2
SW3
BB_OUT
LDO2
LDO3
LDO4
1V TO 1.2V
V
IN
1.8V
0.8V TO 1V
3.3V
1.2V
1.8V
2.8V
always-active LDO operating. If PWR_ON is HIGH at the
end of one second and the fault condition has cleared, the
LTC3589 will power-up in the same way shown in Figure 8.
Neither IRQ nor the status registers are cleared by the
fault induced shutdown.
ENABLE AND POWER-ON SEQUENCING
Enable Input Pin Operation
The regulator enable input pins facilitate pin-strapping an
output rail to the enable pin of the next regulator in the
desired sequence. The regulator enable inputs normally
have a 0.8V (typical) input threshold. If any enable is driven
HIGH, the remaining enable input thresholds switch to a
more accurate 500mV (typical) threshold.
Figure 11 shows an application circuit for a typical pin-
strapped start-up sequence. Holding ON LOW for 400ms
brings up the WAKE pin that is tied to EN1 and EN3 to en-
able step-down switching regulators 1 and 3. The output
of regulator 1 is tied to EN2 and EN4 which enable step-
down switching regulator 2 and the buck-boost switching
regulator 4. The output of step-down switching regulator 2
is tied to EN_LDO2 and EN_LDO34 to enable LDO2, LDO3
and LDO4. Within five seconds of WAKE going HIGH, the
microprocessor or microcontroller must drive PWR_ON
HIGH to tell LTC3589 that rails are good and to stay in the
power-on state.
PBSTAT
WAKE
PWR_ON
3589 F08
ON(PB)
µC/µP CONTROL
50ms
5 SEC
50ms - LTC3589
2ms - LTC3589-1/LTC3589-2
PBSTAT
WAKE
3589 F07
ON(PB)
50ms
<5 SEC
PWR_ON
µC/µP CONTROL
50ms - LTC3589
2ms - LTC3589-1/
LTC3589-2