LTC3589/LTC3589-1/ LTC3589-2 8-Output Regulator with Sequencing and I2C Features n n n n n n n n n n n n Description Triple I2C Adjustable High Efficiency Step-Down DC/ DC Converters: 1.6A, 1A/1.2A, 1A/1.2A High Efficiency 1.2A Buck-Boost DC/DC Converter Triple 250mA LDO Regulators Pushbutton ON/OFF Control with System Reset Flexible Pin-Strap Sequencing Operation I2C and Independent Enable Control Pins Power Good and Reset Outputs Dynamic Voltage Scaling and Slew Rate Control Selectable 2.25MHz or 1.
LTC3589/LTC3589-1/ LTC3589-2 Table of Contents Features............................................................................................................................. 1 Applications........................................................................................................................ 1 Typical Application ................................................................................................................ 1 Description................................................
LTC3589/LTC3589-1/ LTC3589-2 Absolute Maximum Ratings (Notes 1, 3) VIN, DVDD, SW1, SW2, SW3, SW4AB, SW4CD..... –0.3V to 6V SW1, SW2, SW3, SW4AB, SW4CD (Transients < 1µs, Duty Cycle < 5%)................ –2V to 7V PVIN1, PVIN2, PVIN3, PVIN4................ –0.3V to VIN + 0.3V VIN_LDO2, VIN_LDO34.......................... –0.3V to VIN + 0.
LTC3589/LTC3589-1/ LTC3589-2 Electrical Characteristics The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = PVIN1 = PVIN2 = PVIN3 = PVIN4 = VIN_LDO2 = VIN_LDO34 = DVDD = 3.8V. All regulators disabled unless otherwise noted.
LTC3589/LTC3589-1/ LTC3589-2 Electrical Characteristics The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = PVIN1 = PVIN2 = PVIN3 = PVIN4 = VIN_LDO2 = VIN_LDO34 = DVDD = 3.8V. All regulators disabled unless otherwise noted.
LTC3589/LTC3589-1/ LTC3589-2 Electrical Characteristics The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = PVIN1 = PVIN2 = PVIN3 = PVIN4 = VIN_LDO2 = VIN_LDO34 = DVDD = 3.8V. All regulators disabled unless otherwise noted.
LTC3589/LTC3589-1/ LTC3589-2 Electrical Characteristics The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = PVIN1 = PVIN2 = PVIN3 = PVIN4 = VIN_LDO2 = VIN_LDO34 = DVDD = 3.8V. All regulators disabled unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS tSU_STA Repeated Start Condition Set-Up Time 0.6 µs tSU_STO Stop Condition Set-Up Time 0.
LTC3589/LTC3589-1/ LTC3589-2 Electrical Characteristics The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = PVIN1 = PVIN2 = PVIN3 = PVIN4 = VIN_LDO2 = VIN_LDO34 = DVDD = 3.8V. All regulators disabled unless otherwise noted. SYMBOL PARAMETER CONDITIONS VRSTO RSTO Output Low Voltage I RSTO = 3mA I RSTO RSTO Output High Leakage Current VRSTO = 3.
LTC3589/LTC3589-1/ LTC3589-2 Typical Performance Characteristics 14 Standby IVIN vs VIN 250 12 VIN = 3.8V, TA = 25°C, unless otherwise noted. LDO2 to LDO4 IVIN vs VIN 900 600 ENABLE TWO LDOs 150 IVIN (µA) IVIN (µA) IVIN (µA) 6 ENABLE ONE LDO 100 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 ENABLE ONE BUCK 400 20 200 3.0 3.5 4.0 VIN (V) 4.5 5.0 100 STANDBY (ONLY LDO1 ON) 0 1.0 PERCENT CHANGE (%) 2.25 2.05 2.00 1.
LTC3589/LTC3589-1/ LTC3589-2 Typical Performance Characteristics 90 BURST 80 70 60 PWM MODE 50 40 30 20 0 0.01 0.1 1 10 100 LOAD CURRENT (mA) 90 70 60 50 FORCED CONTINUOUS 40 30 0 0.01 0.1 1 10 100 LOAD CURRENT (mA) FORCED CONTINUOUS 40 30 PULSE-SKIPPING 0.1 1 10 100 LOAD CURRENT (mA) 1000 3589 G12 Buck-Boost RDS(ON) vs Temperature 0.25 0.40 0.35 BURST 70 PULSESKIPPING 60 50 0.20 0.30 FORCED CONTINUOUS 40 RDS(ON) (Ω) EFFICIENCY (%) 50 0 0.
LTC3589/LTC3589-1/ LTC3589-2 Typical Performance Characteristics Buck-Boost Switching Regulator Soft-Start VIN = 3.8V, TA = 25°C, unless otherwise noted.
LTC3589/LTC3589-1/ LTC3589-2 Typical Performance Characteristics LDO2, LDO3, LDO4 Dropout Voltage vs Temperature LDO2, LDO3, LDO4 Dropout Voltage vs Load Current LDO2, LDO3, LDO4 Short-Circuit Current vs Temperature 500 DROPOUT VOLTAGE (mV) VLDO = 1.2V 400 300 VLDO = 1.8V 200 VLDO = 3.3V 100 500 400 SHORT-CIRCUIT CURRENT (mA) 500 DROPOUT VOLTAGE (mV) VIN = 3.8V, TA = 25°C, unless otherwise noted. VLDO = 1.2V 300 VLDO = 1.8V 200 100 VLDO = 3.
LTC3589/LTC3589-1/ LTC3589-2 Pin Functions VIN_LDO2 (Pin 1): Power Input for LDO2. This pin should be bypassed to ground with a 1µF or greater ceramic capacitor. LDO2 (Pin 2): Output Voltage of LDO2. Nominal output voltage is set with a resistor feedback divider that servos to an I2C register controlled DAC reference. This pin must be bypassed to ground with a 1µF or greater ceramic capacitor. LDO3 (Pin 3): Output Voltage of LDO3. Nominal output voltage is fixed at 1.8V or 2.8V (LTC3589-1/LTC3589-2).
LTC3589/LTC3589-1/ LTC3589-2 PIN FUNCTIONS ON (Pin 21): Pushbutton Input. A weak internal pull-up forces ON high when left floating. A normally open pushbutton is connected from ON to ground to force a low state on this pin. PBSTAT (Pin 22): Pushbutton Status. Open-drain output to be used for processor interrupts. PBSTAT mirrors the status of ON pushbutton pin. PBSTAT is delayed 50ms from ON pin for debounce. WAKE (Pin 23): System Wake Up.
LTC3589/LTC3589-1/ LTC3589-2 Block Diagram VIN PVIN4 BB_OUT VREF 0.8V TO VIN AT 25mA BUCK-BOOST SW4AB VREF LDO1_STDBY OK LDO1_FB 1.8V TO 5.0V AT 1.2A SW4CD ALWAYS ON LDO1 EN OK BB_FB IRQ PVIN1 ON (PB) BUCK 1 PBSTAT WAKE CONTROL + SEQUENCE EN PWR_ON SW1 OK VSTB VREF DAC BUCK1_FB EN1 EN-PINS EN2 PVIN2 EN-I2C EN3 BUCK 2 EN4 EN_LDO2 EN SW2 0.5V TO VIN AT 1A/1.2A OK EN_LDO34 EN_LDO3 (LTC3589-1/ LTC3589-2) 0.5V TO VIN AT 1.
LTC3589/LTC3589-1/ LTC3589-2 Operation Introduction The LTC3589 is a complete power management solution for portable microprocessors and peripheral devices. It generates a total of eight voltage rails for supplying power to the processor core, SDRAM, system memory, PC cards, always-on real-time clock and HDD functions. Supplying the voltage rails are an always-on low quiescent current 25mA LDO, one 1.6A and two 1A (1.2A for LTC3589-1/ LTC3589-2) step-down regulators, a 1.
LTC3589/LTC3589-1/ LTC3589-2 OPERATION The LTC3589 has flexible options for enabling and sequencing the regulator enables. The regulators are enabled using input pins or the I2C serial port. To define a power-on sequence tie the enable of the first regulator to be powered up to the WAKE pin. Connect the first regulators output to the enable pin of the second regulator, and so on. One or more regulators may be started in any sequence.
LTC3589/LTC3589-1/ LTC3589-2 OPERATION undervoltage threshold in effect for the rest of the LTC3589 circuits. The always-on LDO is used to provide power to a standby microcontroller, real-time clock, or other keepalive circuits. The LDO is guaranteed to support a 25mA load. A 1µF low impedance ceramic bypass capacitor from LDO1_STBY to GND is required for compensation. A power good monitor pulls RSTO LOW for a minimum of 14ms (typical) whenever LDO1_STBY is 8% below its regulation target.
LTC3589/LTC3589-1/ LTC3589-2 OPERATION Table 2. Shows the I2C command register settings used to control LDO2. Table 2.
LTC3589/LTC3589-1/ LTC3589-2 OPERATION Step-Down Switching Regulators Operating Modes Output Voltage Programming The step-down switching regulators include three possible operating modes to meet the noise and power needs of a variety of applications. Each of the step-down converters uses a dynamically slewing DAC output for its reference.
LTC3589/LTC3589-1/ LTC3589-2 OPERATION due to the continuous operation of the MOSFET switch and rectifier. Since the inductor current is allowed to be negative in forced continuous operation the step-down switching regulator has the ability to sink output current. The LTC3589 automatically forces the step-down switching regulator into forced continuous mode when dynamically slewing the DAC voltage reference down.
LTC3589/LTC3589-1/ LTC3589-2 OPERATION while powering up following a fault condition. A soft-start cycle is not triggered by a change of operating modes or a dynamic voltage slew. During soft-start the converter is forced to pulse-skipping mode regardless of the settings in the SCR1 command register. Table 6. Step-Down Switching Regulator 2 Command Register Settings COMMAND REGISTER[BIT] SCR1[3-2] VALUE SETTING Table 7.
LTC3589/LTC3589-1/ LTC3589-2 OPERATION quency to 1.125MHz. Selection of the operating frequency is determined by desired efficiency, component size and converter duty cycle. Operation at lower frequency improves efficiency by reducing internal gate charge and switching losses but requires larger inductance and capacitance values for comparable output ripple voltage. The lowest duty cycle of the stepdown switching regulator is determined by the converters minimum on-time.
LTC3589/LTC3589-1/ LTC3589-2 OPERATION Buck-Boost Switching Regulator Output Voltage Programming Set the output voltage of the LTC3589 buck-boost switching regulator using an external resistor divider connected from BB_OUT to the feedback pin BB_FB and to GND, as shown in Figure 4. R1 VBB _OUT = 0.8 • 1+ (V) R2 The value of R1 plays a role in setting the dynamics of the buck-boost voltage mode control loop.
LTC3589/LTC3589-1/ LTC3589-2 OPERATION PVIN4 SW4AB SW4CD A D B C EN MODE BB_OUT PWM CONTROL R1 22µF BB_FB – 0.8V R2 + 3589 F04 Figure 4. Buck-Boost Switching Regulator Application Circuit Table 9. Inductors for Step-Down Switching Regulators 2 and 3 PART NUMBER VALUE (µH) DCR (Ω) MAX DC CURRENT (A) SIZE (mm) W × L × H Coilcraft XPL4020-102ML XPL4020-152ML XPL4020-472ML 1.0 1.5 4.7 0.029 0.036 0.130 4.00 3.60 1.90 4.2 × 4.2 × 2.0 4.2 × 4.2 × 2.0 4.2 × 4.2 × 2.
LTC3589/LTC3589-1/ LTC3589-2 OPERATION Operating Modes Table 10 shows the I2C command registers used to control the operating modes of the LTC3589 buck-boost converter. When command register SCR1 bit 6 is LOW, the LTC3589 buck-boost switching regulator operates in a fixed frequency pulse width modulation mode using voltage mode feedback control.
LTC3589/LTC3589-1/ LTC3589-2 OPERATION Inductor Selection Table 10. Buck-Boost Command Register Settings Inductor selection criteria for the buck-boost are similar to those given for the step-down switching regulators. The buck-boost converter is designed to work with inductors in the range of 1µH to 3.3µH. For most applications use a 1.5µH inductor.
LTC3589/LTC3589-1/ LTC3589-2 OPERATION Capacitor Selection Table 13. Slewing DAC Command Register Control Summary Low ESR ceramic capacitors should be used at both the output and input supply of the buck-boost switching regulator. Only X5R or X7R ceramic capacitors should be used because they retain their capacitance over wider voltage and temperature ranges than other ceramic types. A 22µF capacitor is sufficient for the buck-boost switching regulator output.
LTC3589/LTC3589-1/ LTC3589-2 OPERATION Writing a 0 or 1 to the odd bits of voltage change control register VCCR selects DAC output voltages V1 or V2, respectively. A slew of the DAC is initiated by writing a 1 to an even bit of register VCCR. The DAC output will slew to either voltage, V1 or V2, as selected by the odd bits of register VCCR. Slew begins when the I2C STOP condition is detected. At the end of the slewing operation the GO bits in command register VCCR are cleared.
LTC3589/LTC3589-1/ LTC3589-2 OPERATION power-up state (PUP) until ON is held LOW for at least 400ms (PB400ms) or until PWR_ON is activated by the PWR_ON pin. When the controller enters the PUP state the open-drain WAKE pin releases HIGH. The WAKE pin is typically used to enable the first regulator in a start-up sequence. The pushbutton state will stay in PUP for five seconds before transitioning to the power-on (PON) state.
LTC3589/LTC3589-1/ LTC3589-2 OPERATION ON(PB) PBSTAT 400ms WAKE <5 SEC µC/µP CONTROL PWR_ON 3589 F06 Figure 6. Power-Up Using the Pushbutton Enable and Power-On Sequencing Enable Input Pin Operation <5 SEC ON(PB) 50ms PBSTAT WAKE µC/µP CONTROL PWR_ON 50ms - LTC3589 2ms - LTC3589-1/ LTC3589-2 3589 F07 Figure 7. Power Down Using Pushbutton ON(PB) PBSTAT 50ms - LTC3589 2ms - LTC3589-1/LTC3589-2 WAKE PWR_ON 5 SEC µC/µP CONTROL 50ms 3589 F08 Figure 8.
LTC3589/LTC3589-1/ LTC3589-2 OPERATION Figure 12 shows the start-up timing for the application shown in Figure 11. There is a 200µs (typical) delay between the enable pin and the internal enable signal to each regulator. WAKE V1 1.2V 0.5V 200µs 1V V3 V2 0.5V 1.8V 200µs 3.3V V4 200µs LDO2 LDO3 1.2V less of the status of PWR_ON and WAKE. Writing a 1 to a regulator’s keep-alive bit in its dynamic target voltage register will keep a regulator alive when the LTC3589 is in standby (POFF) mode.
LTC3589/LTC3589-1/ LTC3589-2 OPERATION RSTO Pin Function The RSTO (reset output) pin is an open-drain output for use as a power-on reset signal. It is pulled LOW at initial power until LDO1 is within 8% of its target and the initial one second start-up timer is finished. RSTO remains HIGH during normal operation and will be pulled low if LDO1 loses regulation for more than 25µs or a pushbutton hard reset is initiated. RSTO is released high 14ms after LDO1 returns to regulation.
LTC3589/LTC3589-1/ LTC3589-2 OPERATION If any enabled regulator output falls more than 7% low for longer than 25µs PGOOD is pulled LOW and a corresponding status bit in the PGSTAT register is set to 0. The PGOOD pin and PGSTAT status bit remain LOW for as long as the low voltage condition persists plus 250µs. An extended low output rail causing the PGOOD pin to be LOW for longer than 14ms defines a PGOOD timeout fault condition that triggers a hard reset if not masked in I2C register bit SCR2[7].
LTC3589/LTC3589-1/ LTC3589-2 OPERATION Figure 17 shows the timing of the IRQ pin and IRQSTAT status register following a fault induced hard shutdown event. When a fault occurs, IRQ is latched LOW and bit IRQSTAT[3], IRQSTAT[5], or IRQSTAT[7] is set. IRQ remains LOW until the CLIRQ command is issued. When the CLIRQ command has been issued, the IRQSTAT status bit remains set for the one second enable inhibit time or as long as the fault condition persists, whichever is longer.
LTC3589/LTC3589-1/ LTC3589-2 OPERATION I2C Operation commands the LTC3589 to act upon its new command set. A STOP condition is sent by the master by transitioning SDA from LOW to HIGH while SCL is HIGH. The bus it then free for communication with another I2C device. I2C Interface The LTC3589 communicates with a bus master using the standard I2C 2-wire interface. The two bus lines, SDA and SCL, must be HIGH when the bus is not in use.
LTC3589/LTC3589-1/ LTC3589-2 OPERATION I2C Sub-Addressed Writing The LTC3589 has 14 command registers for control inputs. They are accessed by the I2C port via a sub-addressed writing system. Each write cycle of the LTC3589 consists of a series of three or more bytes beginning with the LTC3589 write address. The second byte is the sub address of the command register being written to. The sub address is a pointer to the register where the data in the third byte will be stored.
LTC3589/LTC3589-1/ LTC3589-2 OPERATION Table 17.
LTC3589/LTC3589-1/ LTC3589-2 OPERATION Table 17. LTC3589 Command Register Table REG NAME B[7] 0x12 SCR2 LTC3589-2 0x20 VCCR B[6] B[5] B[4] B[3] B[2] B[1] Mask PGOOD LDO4 Hard Start-Up: Shutdown: LDO4 Start-Up: LDO4 Start-Up: LDO4 Start-Up: LDO4 Start-Up: LDO4 Start-Up: LDO4 Start-Up: 0 = Inhibit PGOOD Timeout Hard Shutdown.
LTC3589/LTC3589-1/ LTC3589-2 OPERATION Table 17. LTC3589 Command Register Table REG NAME B[7] 0x26 B2DTV1 Unused B[6] B[5] B[4] PGOOD Mask: Step-Down Switching Regulator 2 Feedback Reference Input (V1) 0 = PGOOD Low When Slewing 00000 = 362.5mV 11001 = 675mV 11111 = 750mV 12.5mV Step Size 1 = PGOOD Not Forced Low When Slewing.
LTC3589/LTC3589-1/ LTC3589-2 OPERATION Table 17. LTC3589 Command Register Table REG NAME B[7] 0x33 L2DTV2 LDO4 Control LDO4 Output Voltage: MODE: 00 = 2.8V 0 = LDO4 Enable with 01 = 2.5V 10 = 1.8V EN_LDO34 11 = 3.3V 1 = LDO4 Enable with OVEN[6] 00000 = 362.5mV 11001 = 675mV 11111 = 750mV 12.5mV Step Size L2DTV2 Unused LDO4 Output Voltage: LDO 2 Feedback Reference Input (V2) 00 = 1.2V 01 = 1.8V 10 = 2.5V 11 = 3.2V 00000 = 362.5mV 11001 = 675mV 11111 = 750mV 12.
LTC3589/LTC3589-1/ LTC3589-2 OPERATION LDO2 and step-down switching regulators 1 to 3 each have a pair of control bits in the voltage change control register VCCR. The reference select bit selects which of two 5-bit words are used as inputs to the regulators feedback reference DAC inputs. The slew GO bit initiates a DAC slew to the voltage selected by the reference select bit. When the slew is complete, the slew GO bits are reset LOW.
LTC3589/LTC3589-1/ LTC3589-2 OPERATION The power dissipated by an LDO regulator is estimated by: PD(LDOX) = (VIN(LDOX) – V LDOX )• I LDOX Where VLDOX is the programmed output voltage, VIN(LDOX) is the LDO supply voltage, and ILDOX is the output load current. If one of the switching regulator outputs is used as an LDO supply voltage, remember to include the LDO supply current in the switching regulator load current for calculating power loss.
LTC3589/LTC3589-1/ LTC3589-2 Applications Information The LTC3589 is optimized to support several families of advanced portable applications processors including the Marvell PXA3xx and PXA168 Xscale processors, the Freescale i.MX family including the new i.MX53 and i.MX51, the TI OMAP processors utilizing their Smart reflex, and many additional ARM processors.
LTC3589/LTC3589-1/ LTC3589-2 Applications Information Earlier i.MX family processors such as the i.MX31 included two VSTB pins used for controlling the regulator outputs for a low voltage standby mode, nominal voltage run mode, and a higher voltage overdrive mode. The LTC3589 can be used with these processors using the VSTB input pin to select between run and standby voltages and using minimal software overhead to set the overdrive voltage in I2C command registers.
LTC3589/LTC3589-1/ LTC3589-2 Typical Application 10µF VIN 10µF 37 VIN PVIN1 SW1 VRTC 1.3V 25mA 36 1µF LDO1_STDBY BUCK1_FB 6 7 100k 35 1µH 100k 39 10µF PVIN2 LDO1_FB 158k LTC3589-2 SW2 BUCK2_FB IMX_LDO_1V8 10 WAKE 11 SW2_VCC 13 DDR_1V5 14 9 18 PWR_ON 20 PVIN3 EN1 EN2 SW3 EN3 1.5µH BUCK3_FB EN_LDO2 EN_LDO3 10µF PVIN4 PWR_ON BB_FB SW4AB 1.3V 22µF 2.2µH 2.5V 1.2A 10µF 10pF 22µF 100k VI-O 3.35V 1.
LTC3589/LTC3589-1/ LTC3589-2 Typical Application VIN 10µF VIN PVIN1 SW1 VRTC 1.2V 25mA 36 1µF 6 7 VCORE 0.647V TO 1.34V 1.6A 1µH 604k LDO1_STDBY BUCK1_FB LDO1_FB 1.02M LTC3589 SW2 VSOC VSRAM 9.09k BUCK2_FB 10k 10k VCORE WAKE 9.09k 10k PWR_ON 10 11 13 14 9 18 20 PVIN3 EN1 EN2 EN3 EN4 EN_LDO2 EN_LDO34 PWR_ON SW3 PVIN4 BB_OUT 21 25 VSRAM/DDR 1.8V 1A 10pF BB_FB 22µF 33 27 26 NVCC_EMI_DRAM NVCC_CNTL_EMI NVCC_PER2,3,4,5,6,8,9 NVCC_EMI(NAND+EMI) 422k 10µF VSOC 0.676V to 1.
LTC3589/LTC3589-1/ LTC3589-2 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UJ Package 40-Lead Plastic QFN (6mm × 6mm) (Reference LTC DWG # 05-08-1728 Rev Ø) 0.70 ±0.05 6.50 ±0.05 5.10 ±0.05 4.42 ±0.05 4.50 ±0.05 (4 SIDES) 4.42 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 6.00 ± 0.10 (4 SIDES) 0.75 ± 0.05 R = 0.10 TYP R = 0.
LTC3589/LTC3589-1/ LTC3589-2 Revision History REV DATE DESCRIPTION A 9/10 Removed 0V from LDO4 on Block Diagram 15 B 12/10 Updated Part Marking in Order Information section 3 C 02/11 LTC3589-1 part added.
LTC3589/LTC3589-1/ LTC3589-2 Typical Application Integrated Power IC for Mobile µProcessor System with USB/Automotive Battery Charger C7 0.47µF VIN VIN R2 150k 5 10 PG VC 7 GND FB BD SYNC 11 9 1 USB OVGATE 2 1 15-17 TO µC 8 TO µC 4 R7 100k T 5 R8 100k R11 499k 8 VBUS 18 VC WALL 19 OVSENS IDGATE D0–D2 BAT LTC4098 CHRG 68k 13 14 VB3 VB2 10 VBB 68k 9 18 23 20 11 68k 68k R9 2.94k VBB GND BATSENS 9, 21 6 CLPROG PROG 3 7 C3 0.
