Datasheet

LTC3588-1
7
35881fa
PIN FUNCTIONS
PZ1 (Pin 1): Input connection for piezoelectric element or
other AC source (used in conjunction with PZ2).
PZ2 (Pin 2): Input connection for piezoelectric element or
other AC source (used in conjunction with PZ1).
CAP (Pin 3): Internal rail referenced to V
IN
to serve as gate
drive for buck PMOS switch. A 1µF capacitor should be
connected between CAP and V
IN
. This pin is not intended
for use as an external system rail.
V
IN
(Pin 4): Rectifi ed Input Voltage. A capacitor on this
pin serves as an energy reservoir and input supply for the
buck regulator. The V
IN
voltage is internally clamped to a
maximum of 20V (typical).
SW (Pin 5): Switch Pin for the Buck Switching Regulator.
A 10µH or larger inductor should be connected from SW
to V
OUT
.
V
OUT
(Pin 6): Sense pin used to monitor the output volt-
age and adjust it through internal feedback.
V
IN2
(Pin 7): Internal low voltage rail to serve as gate drive
for buck NMOS switch. Also serves as a logic high rail for
output voltage select bits D0 and D1. A 4.7µF capacitor
should be connected from V
IN2
to GND. This pin is not
intended for use as an external system rail.
D1 (Pin 8): Output Voltage Select Bit. D1 should be tied
high to V
IN2
or low to GND to select desired V
OUT
(see
Table 1).
D0 (Pin 9): Output Voltage Select Bit. D0 should be tied
high to V
IN2
or low to GND to select desired V
OUT
(see
Table 1).
PGOOD (Pin 10): Power good output is logic high when
V
OUT
is above 92% of the target value. The logic high is
referenced to the V
OUT
rail.
GND (Exposed Pad Pin 11): Ground. The Exposed Pad
should be connected to a continuous ground plane on the
second layer of the printed circuit board by several vias
directly under the LTC3588-1.
BLOCK DIAGRAM
35881 BD
D1, D0
PZ2
PZ1
V
IN
UVLO
BUCK
CONTROL
INTERNAL RAIL
GENERATION
2
BANDGAP
REFERENCE
SLEEP
PGOOD
COMPARATOR
CAP
SW
GND
PGOOD
V
IN2
V
OUT
20V
5
3
7
11
10
6
8, 9
2
1
4