Datasheet

LTC3588-1
12
35881fa
APPLICATIONS INFORMATION
PGOOD Signal
The PGOOD signal can be used to enable a sleeping
microprocessor or other circuitry when V
OUT
reaches
regulation, as shown in Figure 5. Typically V
IN
will be
somewhere between the UVLO thresholds at this time and
a load could only be supported by the output capacitor.
Alternatively, waiting a period of time after PGOOD goes
high would let the input capacitor accumulate more energy
allowing load current to be maintained longer as the buck
effi ciently transfers that energy to the output. While active,
a microprocessor may draw a small load when operating
sensors, and then draw a large load to transmit data.
Figure 5 shows the LTC3588-1 responding smoothly to
such a load step.
Input and Output Capacitor Selection
The input and output capacitors should be selected
based on the energy needs and load requirements of the
application. In every case the V
IN
capacitor should be
rated to withstand the highest voltage ever present at V
IN
.
For 100mA or smaller loads, storing energy at the input
takes advantage of the high voltage input since the buck
can deliver 100mA average load current effi ciently to the
output. The input capacitor should then be sized to store
enough energy to provide output power for the length of
time required. This may involve using a large capacitor,
letting V
IN
charge to a high voltage, or both. Enough energy
should be stored on the input so that the buck does not
reach the UVLO falling threshold which would halt energy
transfer to the output. In general:
P
LOAD
t
LOAD
=
1
2
ηC
IN
V
IN
2
− V
UVLOFALLING
2
()
V
UVLOFALLING
≤ V
IN
≤ V
SHUNT
The above equation can be used to size the input capaci-
tor to meet the power requirements of the output for the
desired duration. Here η is the average effi ciency of the
buck converter over the input range and V
IN
is the input
voltage when the buck begins to switch. This equation
may overestimate the input capacitor necessary since load
current can deplete the output capacitor all the way to the
lower PGOOD threshold. It also assumes that the input
source charging has a negligible effect during this time.
The duration for which the regulator sleeps depends on
the load current and the size of the output capacitor. The
sleep time decreases as the load current increases and/or
as the output capacitor decreases. The DC sleep hysteresis
window is ±12mV around the programmed output volt-
age. Ideally this means that the sleep time is determined
by the following equation:
t
SLEEP
= C
OUT
24mV
I
LOAD
35881 F05a 35881 F05b
PZ1
V
IN
CAP
V
IN2
D1
D0
PZ2
PGOOD
SW
V
OUT
LTC3588-1
MICROPROCESSOR
GND
1µF
6V
4.7µF
6V
10µF
25V
47µF
6V
10µH
3.3V
EN
CORE
GND
T
X
250µs/DIV
V
IN
= 5V
L = 10µH, C
OUT
= 47µF
LOAD STEP BETWEEN 5mA and 55mA
OUTPUT
VOLTAGE
20mV/DIV
AC-COUPLED
LOAD
CURRENT
25mA/DIV
5mA
MIDE V21BL
Figure 5. 3.3V Piezoelectric Energy Harvester Powering a Microprocessor
with a Wireless Transmitter and 50mA Load Step Response