Datasheet

LTC3577/LTC3577-1
45
3577fa
OPERATION
Power-Up via External Power Timing
The timing diagram, Figure 20, shows the LTC3577 power-
ing up through application of the external power (V
BUS
or
WALL). For this example the pushbutton circuitry starts
in the POFF or HR state with a battery connected and all
buck disabled. 100ms after WALL or V
BUS
application the
WAKE output goes Hi-Z for 5 seconds. The 100ms delay
time allows the applied supply to settle. WAKE going
Hi-Z sequences buck1-3 up in numerical order. WAKE
will stay Hi-Z if the PWR_ON input is driven high before
the 5 seconds PUP period is over. If PWR_ON is low or
goes low after the 5 second period, WAKE will go low and
buck1-3 will be shut down together. PG_DCDC is asserted
once all enabled bucks are within 8% of their regulation
voltage for 230ms.
The LDOs and LED backlight can be enabled and disabled
via I
2
C any time after entering the PUP1, PUP2 or PON
state. The PWR_ON input can be driven via a P/C or one
of the buck outputs through a high impedance (100kΩ
typ) to keep the bucks enabled as described above.
Without a battery present initial power application causes
a power on reset which puts the pushbutton circuitry in
the PDN2 state and subsequently the HR state 1 second
later. In this case the pushbutton must be applied to enter
the PUP1 state after initial power application.
Power-Up via PWR_ON Timing
The timing diagram, Figure 21, shows the LTC3577
powering up by driving PWR_ON high. For this example
the pushbutton circuitry starts in the POFF or HR state
with a battery connected and all bucks disabled. 50ms
after PWR_ON goes high the WAKE output goes Hi-Z for
5 seconds. WAKE going Hi-Z sequences buck1-3 up in
numerical order. WAKE will stay Hi-Z as long as PWR_ON
is high at the end of the 5 second PUP period. If PWR_ON
is low or goes low after the 5 second period, WAKE will
go low and buck1-3 will be shut down together. PG_DCDC
is asserted once all enabled bucks are within 8% of their
regulation voltage for 230ms.
The LDOs and LED backlight can be enabled and disabled
via I
2
C any time after entering the PUP1, PUP2 or PON
state.
Powering up via PWR_ON is useful for applications
containing an always on C. This allows the C to power
the application up and down for house keeping and other
activities outside the user’s control.
BAT
PBSTAT
WAKE
100ms
230ms
1 2 3
BUCKS SEQUENCE UP
BUCK1-3
PG_DCDC
PWR_ON
STATE POFF/HR PUP2/PUP1 PON
3755 F20
V
BUS
ON (PB)
5SEC
Figure 20. Power-Up via External Power Timing
PBSTAT
PWR_ON
WAKE
BUCK1-3
PG_DCDC
STATE POFF/HR PUP2/PUP1 PON
BAT
ON (PB)
230ms
3577 F21
1 2 3
BUCKS SEQUENCE UP
5Oms
5SEC
Figure 21. Power-Up via PWR_ON Timing