Datasheet

LTC3569
10
3569fe
For more information www.linear.com/LTC3569
operaTion
Introduction
The LTC3569 contains three constant-frequency, current
mode buck DC/DC regulators. Both the P-channel and
synchronous rectifier (N-channel) switches are internal
to each buck. The operating frequency is determined by
the value of the R
T
resistor, or is fixed to 2.25MHz by pull-
ing the R
T
pin to SV
IN
, or is synchronized to an external
oscillator tied to the MODE pin. Users may select pulse-
skipping or Burst Mode operation to trade off output ripple
for efficiency. Independent programmable reference levels
allow the LTC3569 to suit a variety of applications.
The LTC3569 offers different power levels, a single 1.2A
buck as well as two 600mA bucks. These three bucks
may be configured in different parallel configurations,
for versatile high current operation. The power stage of
buck 2 can be configured as a slave to buck 1, by pulling
FB2 to SV
IN
. The power stage of buck 3, can be configured
to be a slave to buck 2, by pulling the FB3 pin to SV
IN
. To
enable the slave power stage, pull the respective EN pin
high. However if the master is disabled, the slave power
stage is Hi-Z.
Each of the buck regulators supports 100% duty cycle
operation (low dropout mode) when their input voltage
drops very close to their output voltage. The switching
regulators also include soft-start to limit inrush current
when powering on, and short-circuit current protection.
Main Control Loop
During normal operation, the top power switch (P-chan-
nel MOSFET) is turned on at the beginning of a clock
cycle. The P-channel current ramps up as the inductor
charges. The peak inductor current is controlled by the
internally compensated error amplifier output, I
TH
. The
current comparator (PCOMP) turns off the P-channel and
turns on the N-channel synchronous rectifier when the
inductor current reaches the I
TH
level minus the offset of
the slope compensation ramp. The energy stored in the
inductor continues to flow through the bottom switch
(N-channel) and into the load until either the inductor
current approaches zero, or the next clock cycle begins.
If the inductor current approaches zero the N comparator
Figure 2. Buck Block Diagram
3569 F02
–
+
–
+
I
LIM
I
LIM
N
COMP
SWITCHING
LOGIC,
BLANKING,
ANTI SHOOT-THRU
S Q
R
P-LATCH
CLK
–
+
SLOPE
P
VIN
P-CHANNEL
N-CHANNEL
SW
P
GND
ON
SLAVE
SLAVE
P
ON
N
OFF
FROM MASTER
SLEEP
BURST
CLAMP
MODE
I
TH
EA
SOFT
START
SLAVE
SD
ON
V
REF
V
FB
S
VIN
EA
SLAVE
V
REF
PGOOD
NOR
NAND
GATE
NOR
P COMP