Datasheet

LTC3568
16
3568fa
Typical applicaTions
Low Output Voltage, 2mm Height Buck Regulator Efficiency vs Load Current
PS
PV
IN
LTC3568
PGOOD PGOOD
SW
SV
IN
SYNC/MODE
V
FB
I
TH
SHDN/R
T
L1
1.7µH
V
OUT
1.2V/1.5V/1.8V
AT 1.8A
V
IN
2.5V
TO 5.5V
SGND PGND
SGND
GND
SGND
FC
PGND
R5
100k
C4 47pF
R4
324k
R3
13k
R1C
787k
R2
402k
3568 TA04
C3
1000pF
C1
22µF
C1: TAIYO YUDEN JMK325BJ226MM
C2: TAIYO YUDEN JMK325BJ476MM
L1: SUMIDA CDRH2D18/HP1R7
C2
47µF
x2
R1B
453k
1.2V1.5V
R1A
316k
1.8V
R
S1
1M
R
S2
1M
BM
LOAD CURRENT (mA)
EFFICIENCY (%)
95
90
85
80
75
70
1 100 1000 10000
3568 TA05
10
V
IN
= 3.3V
Burst Mode OPERATION
f
O
= 1MHz
V
OUT
= 1.2V
V
OUT
= 1.5V
V
OUT
= 1.8V
package DescripTion
3.00 p0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 p 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 p 0.10
(2 SIDES)
0.75 p0.05
R = 0.125
TYP
2.38 p0.10
(2 SIDES)
15
106
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DD) DFN REV C 0310
0.25 p 0.05
2.38 p0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 p0.05
(2 SIDES)
2.15 p0.05
0.50
BSC
0.70 p0.05
3.55 p0.05
PACKAGE
OUTLINE
0.25 p 0.05
0.50 BSC
PIN 1 NOTCH
R = 0.20 OR
0.35 s 45o
CHAMFER
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev C)