Datasheet

11
LTC3564
3564f
Output Voltage Programming
In the adjustable version, the output voltage is set by a
resistive divider according to the following formula:
VV
R
R
OUT
=+
⎛
⎝
⎜
⎞
⎠
⎟
06 1
2
1
.
(2)
The external resistive divider is connected to the output,
allowing remote voltage sensing as shown in Figure 2.
1. The V
IN
quiescent current is due to two components:
the DC bias current as given in the electrical character-
istics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate is
switched from high to low to high again, a packet of
charge, dQ, moves from V
IN
to ground. The resulting
dQ/dt is the current out of V
IN
that is typically larger than
the DC bias current. In continuous mode, I
GATECHG
=
f(Q
T
+ Q
B
) where Q
T
and Q
B
are the gate charges of the
internal top and bottom switches. Both the DC bias and
gate charge losses are proportional to V
IN
and thus
their effects will be more pronounced at higher supply
voltages.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
, and external inductor R
L
. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R
DS(ON)
and the duty cycle
(DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1 – DC)
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses in LTC3564 circuits: V
IN
quiescent current and I
2
R
losses. The V
IN
quiescent current loss dominates the
efficiency loss at very low load currents whereas the I
2
R
loss dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence as illustrated in Figure 3.
APPLICATIO S I FOR ATIO
WUU
U
Figure 3. Power Lost vs Load Current
Figure 2. Setting the LTC3564 Output Voltage
LOAD CURRENT (A)
0.1
0.0001
POWER LOSS (W)
0.01
1
1 10 100 1000 10000
3564 F03
0.001
0.1
V
OUT
= 1.2V
V
OUT
= 1.5V
V
OUT
= 1.8V
V
IN
= 3.6V
V
FB
GND
LTC3564
0.6V ≤ V
OUT
≤ 5.5V
R2
R1
3564 F02