Datasheet

LTC3561
12
3561f
For cost reasons, a ceramic capacitor will be used. C
OUT
selection is then based on load step droop instead of ESR
requirements. For a 5% output droop:
C
A
MHz V
F
OUT
≈ =µ25
1
1525
20.
•( %• . )
The closest standard value is 22µF. Since the output
impedance of a Li-Ion battery is very low, C
IN
is typically
10µF. In noisy environments, decoupling SV
IN
from PV
IN
with an R6/C8 filter of 1Ω/0.1µF may help, but is typically
not needed.
The output voltage can now be programmed by choosing
the values of R1 and R2. To maintain high efficiency, the
current in these resistors should be kept small. Choosing
2µA with the 0.8V feedback voltage makes R1~400k. A
close standard 1% resistor is 412k and R2 is then 887k.
The compensation should be optimized for these compo-
nents by examining the load step response but a good
place to start for the LTC3561 is with a 13kΩ and 1000pF
filter. The output capacitor may need to be increased
depending on the actual undershoot during a load step.
The circuit in Figure 6 shows the complete schematic for
this design example.
Board Layout Considerations
When laying out the printed circuit board, the follow-
ing checklist should be used to ensure proper oper-
ation of the LTC3561. These items are also illustrated
APPLICATIO S I FOR ATIO
WUU
U
graphically in the layout diagram of Figure 5. Check
the following in your layout:
1. Does the capacitor C
IN
connect to the power V
IN
(Pin 5)
and power GND (Pin 4) as close as possible? This
capacitor provides the AC current to the internal power
MOSFETs and their drivers.
2. Are the C
OUT
and L1 closely connected? The (–) plate of
C
OUT
returns current to PGND and the (–) plate of C
IN
.
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C
OUT
and a ground line termi-
nated near SGND (Pin 2). The feedback signal V
FB
should be routed away from noisy components and
traces, such as the SW line (Pin 3), and its trace should
be minimized.
4. Keep sensitive components away from the SW pin. The
input capacitor C
IN
, the compensation capacitor C
C
and
C
ITH
and all the resistors R1, R2, R
T
, and R
C
should be
routed away from the SW trace and the inductor L1.
5. A ground plane is preferred, but if not available, keep the
signal and power grounds segregated with small signal
components returning to the SGND pin at one point
which is then connected to the PGND pin.
6. Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise of
power components. These copper areas should be
connected to one of the input supplies: PV
IN
, PGND,
SV
IN
or SGND.
Figure 5. LTC3561 Layout Diagram (See Board Layout Checklist)
PV
IN
LTC3561
PGND
SW
SV
IN
SGND
V
FB
I
TH
SHDN/R
T
L1
V
IN
V
OUT
R
T
R3R1R2
3561 F06
C3
BOLD LINES INDICATE HIGH CURRENT PATHS
C
IN
C
OUT
C4