Datasheet
LTC3555/LTC3555-X
20
3555fd
OPERATION
Table 2. I
2
C Serial Port Mapping
A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0
Switching Regulator 2
Voltage (See Table 4)
Switching Regulator 3
Voltage (See Table 4)
Disable
Battery
Charger
Switching
Regulator
Modes
(See Table 5)
Enable
Regulator
1
Enable
Regulator
2
Enable
Regulator
3
Input Current
Limit
(See Table 3)
Table 3. USB Current Limit Settings
B1
(I
LIM1
)
B0
(I
LIM0
)
USB SETTING
0 0 1x Mode (USB 100mA Limit)
0 1 10x Mode (Wall 1A Limit)
1 0 Suspend
1 1 5x Mode (USB 500mA Limit)
Table 5. General Purpose Switching Regulator Modes
B6
(SDA)*
B5
(SCL)*
Switching Regulator Mode
0 0 Pulse Skip
0 1 Forced Burst Mode Operation
1 0 LDO Mode
1 1 Burst Mode Operation
*SDA and SCL take on this context only when DV
CC
= 0V.
Table 4. Switching Regulator Servo Voltage
A7 A6 A5 A4 Switching Regulator 2 Servo Voltage
A3 A2 A1 A0 Switching Regulator 3 Servo Voltage
0 0 0 0 0.425V
0 0 0 1 0.450V
0 0 1 0 0.475V
0 0 1 1 0.500V
0 1 0 0 0.525V
0 1 0 1 0.550V
0 1 1 0 0.575V
0 1 1 1 0.600V
1 0 0 0 0.625V
1 0 0 1 0.650V
1 0 1 0 0.675V
1 0 1 1 0.700V
1 1 0 0 0.725V
1 1 0 1 0.750V
1 1 1 0 0.775V
1 1 1 1 0.800V
generated by the slave (LTC3555 family) lets the master
know that the latest byte of information was received.
The acknowledge related clock pulse is generated by the
master. The master releases the SDA line (high) during
the acknowledge clock cycle. The slave-receiver must pull
down the SDA line during the acknowledge clock pulse
so that it remains a stable low during the high period of
this clock pulse.
Slave Address
The LTC3555 family responds to only one 7-bit address
which has been factory programmed to 0001001. The
eighth bit of the address byte (R/W) must be 0 for the
LTC3555 family to recognize the address since it is a write
only device. This effectively forces the address to be eight
bits long where the least significant bit of the address is
0. If the correct seven bit address is given but the R/W bit
is 1, the LTC3555 family will not respond.
Bus Write Operation
The master initiates communication with the LTC3555
family with a START condition and a 7-bit address followed
by the write bit R/W = 0. If the address matches that of the
LTC3555 family, the LTC3555 family returns an acknowl-
edge. The master should then deliver the most significant
data byte. Again the LTC3555 family acknowledges and
the cycle is repeated for a total of one address byte and
two data bytes. Each data byte is transferred to an internal
holding latch upon the return of an acknowledge. After both
data bytes have been transferred to the LTC3555 family,
the master may terminate the communication with a STOP
condition. Alternatively, a REPEAT-START condition can be
initiated by the master and another chip on the I
2
C bus
can be addressed. This cycle can continue indefinitely and
the LTC3555 family will remember the last input of valid
data that it received. Once all chips on the bus have been
addressed and sent valid data, a global STOP condition can