Datasheet

LTC3554/LTC3554-1/
LTC3554-2/LTC3554-3
6
3554123fd
Note 1. Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3554 is tested under pulsed load conditions such that
T
J
≈ T
A
. The LTC3554 are guaranteed to meet specifications from
0°C to 85°C junction temperature. Specifications over the –40°C to
85°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. Note that
the maximum ambient temperature consistent with these specifications
is determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance and other environmental
factors.
The junction temperature (T
J
, in °C) is calculated from the ambient
temperature (T
A
, in °C) and power dissipation (P
D
, in Watts) according to
the formula:
T
J
= T
A
+ (P
D
• θ
JA
)
where
θ
JA
(in °C/W) is the package thermal impedance.
Note 3. This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperatures will exceed 110°C when overtemperature protection is
active. Continuous operation above the specified maximum operating
junction temperature may result in device degradation or failure.
Note 4. V
CC
is the greater of V
BUS
or BAT.
Note 5. Total Battery Drain Current is the sum of I
BATQ
and I
OUT.
For
example, in applications where the buck input (BVIN pin) is connected to
the PowerPath output (V
OUT
pin) such that I
OUT
= I
BVIN
, total battery drain
current = I
BATQ
+ I
BVIN
.
Note 6. hC/10 is expressed as a fraction of programmed full charge
current with specified PROG resistor.
Note 7. The current limit features of this part are intended to protect the
IC from short term or intermittent fault conditions. Continuous operation
above the absolute maximum specified pin current rating may result in
device degradation or failure.
Note 8. FB High, Not Switching
Note 9. V
OUT
not in UVLO.
Note 10. PGOOD threshold is expressed as a percentage difference from
the buck regulation voltage. The threshold is measured with the buck
feedback pin voltage rising.
Note 11. See the Operation section of this data sheet for detailed
explanation of the pushbutton state machine and the effects of each state
on switching regulator and power manager operation.
Note 12. If V
BUS
< V
UVLO
then V
FWD
= 0 and the forward voltage across
the ideal diode is equal to its current times R
DROPOUT
.
PUSHBUTTON INTERFACE ELECTRICAL CHARACTERISTICS
The l denotes
specifications that apply over the full operating junction temperature range, otherwise specifications are at T
A
= 25°C (Note 2).
V
BAT
= 3.8V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t
EXTPWR
Power-Up from USB Present to Power-Up
(PUP1 or PUP2) State
Starting in the Hard Reset (HR) or Power-Off
(POFF) States
100 ms
t
PON_UP
Any PWR_ONx High to Power-On State Starting with Both PWR_ONx Low in the Power-
Off (POFF) State
900 µs
t
PON_DIS
PWR_ONx Low to Buckx Disabled 1 µs
t
PUP
Power-Up (PUP1 or PUP2) State Duration 5 s
t
PDN
Power-Down (PDN1 or PDN2) State
Duration
1 s
t
PGOODH
Bucks in Regulation to PGOOD High All Enabled Bucks within PGOOD Threshold
Voltage
230 ms
t
PGOODL
Bucks Disabled to PGOOD Low All Bucks Disabled 100 µs