Datasheet

LTC3553
31
3553fb
where V
INLDO
is the LDO input supply voltage, V
LDO
is
the LDO regulated output voltage, and I
LDO
is the LDO
load current.
Thus the power dissipated by all regulators is:
P
D(REGS)
= P
D(BUCK)
+ P
D(LDO)
It is not necessary to perform any worst-case power dis-
sipation scenarios because the LTC3553 will automatically
reduce the charge current to maintain the die temperature
at approximately 110°C. However, the approximate ambi-
ent temperature at which the thermal feedback begins to
protect the IC is:
T
A
= 110°C – P
D
• θ
JA
Example: Consider the LTC3553 operating from a wall
adapter with 5V (V
BUS
) providing 400mA (I
BAT
) to charge a
Li-Ion battery at 3.3V (BAT). Also assume P
D(REGS)
= 0.3W,
so the total power dissipation is:
P
D
= (5V – 3.3V) • 400mA + 0.3W = 0.98W
The ambient temperature above which the LTC3553 will be-
gin to reduce the 400mA charge current, is approximately:
T
A
= 110°C – 0.98W • 70°C/W = 41.4°C
The LTC3553 can be used above 41.4°C, but the charge
current will be reduced below 400mA. The charge current
at a given ambient temperature can be approximated by:
P
D
= (110°C – T
A
) / θ
JA
= (V
BUS
– BAT) • I
BAT
+ P
D(REGS)
Thus:
I
BAT
= [(110°C – T
A
) / θ
JA
– P
D(REGS)
]
(V
BUS
– BAT)
Consider the above example with an ambient tem-
perature of 60°C. The charge current will be reduced to
approximately:
I
BAT
= [(110°C – 60°C) / 70°C/W – 0.3W] / (5V – 3.3V)
I
BAT
= (0.71W – 0.3W) / 1.7V = 241mA
Printed Circuit Board Layout
When laying out the printed circuit board, the following
list should be followed to ensure proper operation of the
LTC3553:
1. The Exposed Pad of the package (Pin 21) should connect
directly to a large ground plane to minimize thermal
and electrical impedance.
2. The traces connecting the regulator input supply pins
(BVIN and V
INLDO
) and their respective decoupling
capacitors should be kept as short as possible. The
GND side of each capacitor should connect directly to
the ground plane of the part. This capacitor provides
the AC current to the internal power MOSFETs and their
drivers. It is important to minimize inductance from this
capacitor to the pin of the LTC3553. Connect BVIN to
V
OUT
and V
INLDO
to its input supply through short low
impedance traces.
3. The switching power trace connecting the SW pin to
its inductor should be minimized to reduce radiated
EMI and parasitic coupling. Due to the large voltage
swing of the switching node, sensitive nodes such as
the feedback nodes should be kept far away or shielded
from the switching nodes or poor performance could
result.
4. Connections between the buck regulator inductor and
its output capacitor should be kept as short as possible.
The GND side of the output capacitor should connect
directly to the thermal ground plane of the part.
5. Keep the feedback pin traces (BUCK_FB and LDO_FB)
as short as possible. Minimize any parasitic capacitance
between the feedback traces and any switching node
(i.e., SW and logic signals). If necessary, shield the
feedback nodes with a GND trace.
6. Connections between the LTC3553 PowerPath pins
(V
BUS
and V
OUT
) and their respective decoupling ca-
pacitors should be kept as short as possible. The GND
side of these capacitors should connect directly to the
ground plane of the part.
OPERATION