Datasheet

LTC3553
23
3553fb
The switching regulator input supply should be bypassed
with a 2.2F capacitor. Consult with capacitor manu-
facturers for detailed information on their selection and
specifi cations of ceramic capacitors. Many manufacturers
now offer very thin (<1mm tall) ceramic capacitors ideal
for use in height-restricted designs. Table 2 shows a list
of several ceramic capacitor manufacturers.
LOW DROPOUT LINEAR REGULATOR (LDO)
The LDO regulator supports a load of up to 150mA. The
LDO takes power from the V
INLDO
pin and drives the LDO
output pin with the goal of bringing the LDO_FB feedback
pin voltage to 0.8V. Usually, a resistor divider is connected
between the LDO’s output pin, feedback pin and ground,
in order to close the control loop and program the output
voltage. For stability, the LDO output must be bypassed
to ground with at least a 1F ceramic capacitor.
The LDO is enabled or disabled via the pushbutton interface.
In cases where the LDO is disabled and the PowerPath
is actively driving V
OUT
, an internal pull-down resistor is
switched in to help bring the output to ground. When the
LDO is enabled, a soft-start circuit ramps its regulation
point from zero to fi nal value over a period of roughly
0.2ms, reducing the required V
INLDO
inrush current.
The LDO has two input voltage requirements. The LDO’s
quiescent bias current is supplied through an internal
connection to the USB PowerPath V
OUT
pin. The LDO’s
power input is taken from the V
INLDO
pin. For proper
LDO operation, the V
INLDO
pin must be connected to a
voltage no greater than V
OUT
. For example, V
INLDO
can
be connected to V
OUT
, or to the buck regulator output.
Connecting V
INLDO
to a voltage exceeding V
OUT
may result
in loss of regulation.
OPERATION
Output Voltage Programming
Figure 4 shows the LDO regulator application circuit.
Program the LDO output voltage, V
LDO
, by choosing R1
and R2 such that:
V
LDO
= 0.8V•
R1
R2
+1
⎛
⎝
⎜
⎞
⎠
⎟
Standby Mode LDO Operation (STBY Pin High)
To reduce battery drain current in applications with a
static memory keep-alive or other ultralow quiescent
current state, the LDO may be placed into standby mode
(together with the buck regulator). When the STBY pin is
brought high, LDO bias current is reduced. Unlike the buck
C
OUT
LDO
OUTPUT
LDO_FB
LDO
MP
0.8V R2
GND
R1
0
1
3553 F04
LDO
ENABLE
V
INLDO
Figure 4. LDO Application Circuit