Datasheet

LTC3549
11
3549f
LOAD CURRENT (mA)
0.1000
POWER LOSS (W)
1.0000
0.0100
0.0010
0.1 10 100 1000
3549 F02
0.0001
1
2.5V
3.6V
4.2V
V
IN
BURST
2.5V
3.6V
4.2V
V
IN
PULSE SKIP
V
OUT
= 1.8V
Effi ciency Considerations
The effi ciency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the effi ciency and which change would produce
the most improvement. Effi ciency can be expressed as:
Effi ciency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses in LTC3549 circuits: V
IN
quiescent current and
I
2
R losses. The V
IN
quiescent current loss dominates
the effi ciency loss at very low load currents whereas the
I
2
R loss dominates the effi ciency loss at medium to high
load currents. In a typical effi ciency plot, the effi ciency
curve at very low load currents can be misleading since
the actual power lost is of no consequence, as illustrated
in Figure 2.
1. The V
IN
quiescent current is due to two components: the
DC bias current as given in the Electrical Characteristics
and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
from switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge, dQ, moves
from V
IN
to ground. The resulting dQ/dt is the current out
of V
IN
that is typically larger than the DC bias current. In
continuous mode, I
GATECHG
= f(Q
T
+ Q
B
) where Q
T
and
Q
B
are the gate charges of the internal top and bottom
switches. Both the DC bias and gate charge losses are
proportional to V
IN
and thus their effects will be more
pronounced at higher supply voltages.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
, and external inductor R
L
. In
continuous mode, the average output current fl owing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R
DS(ON)
and the duty cycle
(DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)
(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics.
Thus, to obtain I
2
R losses, simply add R
SW
to R
L
and
multiply the result by the square of the average output
current.
Other losses including C
IN
and C
OUT
ESR dissipative los-
ses and inductor core losses generally account for less
than 2% total additional loss.
APPLICATIO S I FOR ATIO
WUU
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Figure 2. Power Loss vs Load Current