Datasheet

LTC3548
3
3548fc
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3548 is guaranteed to meet specifi ed performance from
0°C to 85°C. Specifi cations over the – 40°C to 85°C operating temperature
range are assured by design, characterization and correlation with
statistical process controls. The LTC3548I is guaranteed to meet specifi ed
performance over the full –40°C to 85°C temperature range.
Note 3: The LTC3548 is tested in a proprietary test mode that connects V
FB
to the output of the error amplifi er.
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 5: T
J
is calculated from the ambient T
A
and power dissipation P
D
according to the following formula: T
J
= T
A
+ (P
D
• θ
JA
).
Note 6: The DFN switch on-resistance is guaranteed by correlation to
wafer level measurements.
The ● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T
A
= 25°C. V
IN
= 3.6V, unless otherwise specifi ed. (Note 2)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ΔV
LOADREG
Output Voltage Load Regulation (Note 3) 0.5 %
I
S
Input DC Supply Current
Active Mode
Sleep Mode
Shutdown
(Note 4)
V
FB1
= V
FB2
= 0.5V
V
FB1
= V
FB2
= 0.63V, MODE/SYNC = 3.6V
RUN = 0V, V
IN
= 5.5V, MODE/SYNC = 0V
700
40
0.1
950
60
1
μA
μA
μA
f
OSC
Oscillator Frequency V
FB
= 0.6V
l
1.8 2.25 2.7 MHz
f
SYNC
Synchronization Frequency 2.25 MHz
I
LIM
Peak Switch Current Limit Channel 1
Peak Switch Current Limit Channel 2
V
IN
= 3V, V
FB
= 0.5V, Duty Cycle <35%
V
IN
= 3V, V
FB
= 0.5V, Duty Cycle <35%
0.95
0.6
1.2
0.7
1.6
0.9
A
A
R
DS(ON)
Top Switch On-Resistance
Bottom Switch On-Resistance
(Note 6)
(Note 6)
0.35
0.30
0.45
0.45
Ω
Ω
I
SW(LKG)
Switch Leakage Current V
IN
= 5V, V
RUN
= 0V, V
FB
= 0V 0.01 1 μA
POR Power-On Reset Threshold V
FB
Ramping Down, MODE/SYNC = 0V –8.5 %
Power-On Reset On-Resistance 100 200 Ω
Power-On Reset Delay 262,144 Cycles
V
RUN
RUN Threshold
l
0.3 1 1.5 V
I
RUN
RUN Leakage Current
l
0.01 1 μA
MODE Mode Threshold Low
Mode Threshold High
0
V
IN
– 0.5
0.5
V
IN
V
V
TYPICAL PERFORMANCE CHARACTERISTICS
T
A
= 25°C unless otherwise specifi ed.
Load Step
Burst Mode Operation Pulse-Skipping Mode
3548 G01
V
IN
= 3.6V
V
OUT
= 1.8V
I
LOAD
= 180mA
CHANNEL 1; CIRCUIT OF FIGURE 3
SW
5V/DIV
V
OUT
20mV/DIV
I
L
200mA/DIV
2μs/DIV
3548 G02
V
IN
= 3.6V
V
OUT
= 1.8V
I
LOAD
= 30mA
CHANNEL 1; CIRCUIT OF FIGURE 3
SW
5V/DIV
V
OUT
10mV/DIV
I
L
200mA/DIV
1μs/DIV
3548 G03
V
IN
= 3.6V
V
OUT
= 1.8V
I
LOAD
= 80mA TO 800mA
CHANNEL 1; CIRCUIT OF FIGURE 3
V
OUT
200mV/DIV
I
L
500mA/DIV
I
LOAD
500mA/DIV
20μs/DIV