Datasheet

LTC3548A
15
3548afa
Figure 2. LTC3548A Layout Diagram (See Board Layout Checklist)
APPLICATIONS INFORMATION
4. Keep sensitive components away from the SW pins.
The input capacitor, C
IN
, and the resistors R1 to R4
should be routed away from the SW traces and the
inductors.
5. A ground plane is preferred, but if not available keep
the signal and power grounds segregated with small-
signal components returning to the GND pin at one
point. Additionally the two grounds should not share
the high current paths of C
IN
or C
OUT
.
6. Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. These copper areas should be connected
to V
IN
or GND.
RUN/SS2 V
IN
V
IN
V
OUT2
V
OUT1
RUN/SS1
POR
SW1
V
FB1
GND
V
FB2
SW2
MODE/SYNC
LTC3548A
C
IN
C4C5
L1
L2
R4 R2
R1
R3
C
OUT2
C
OUT1
3548A F02
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 3. 1mm Height Core Supply
Efficiency vs Load Current
LOAD CURRENT (mA)
1
0
EFFICIENCY (%)
30
20
10
70
60
50
40
100
90
80
10 100 1000
3548A F03b
2.5V
V
IN
= 3.3V
Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
1.8V
RUN/SS2 V
IN
V
IN
2.5V TO 5.5V
V
OUT2
2.5V
400mA
V
OUT1
1.8V
800mA
RUN/SS1
POR
SW1
V
FB1
GND
V
FB2
SW2
MODE/SYNC
LTC3548A
C1
10μF
R5
100k
POWER-ON
RESET
C4 22pFC5 22pF
L1
2.2μH
L2
4.7μH
R4
887k
R2
604k
R1
301k
R3
280k
C3
4.7μF
C2
10μF
3548 F03a
C1, C2, C3: TAIYO YUDEN JMK316BJ106MD
L1: TDK VLF3010AT-2R2M1R0-1
L2: TDK VLF3010AT-4R7MR70-1