Datasheet
LTC3544
3
3544fa
ELECTRICAL CHARACTERISTICS
The ● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T
A
= 25°C. V
IN
= 3.6V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I
S
Input DC Bias Current Active Mode
(Four Regulators Enabled)
V
FB
= 0.7V, I
LOAD
= 0A, 2.25MHz 825 1100 µA
Sleep Mode
(Four Regulators Enabled)
V
FB
= 0.9V, I
LOAD
= 0A, 2.25MHz 70 80 µA
Shutdown 0.1 2 µA
f
OSC
Oscillator Frequency V
IN
= 3V
V
IN
= 2.5V to 5.5V
●
1.8
2.25
2.7
MHz
MHz
V
RUN(HIGH)
RUNx Input High Voltage
●
1.0 V
V
RUN(LOW)
RUNx Input Low Voltage
●
0.3 V
I
SWx
SWx Leakage V
RUN
= 0V, V
SW
= 0V or 5.5V, V
IN
= 5.5V ±0.1 ±1 µA
I
RUNx
RUN Leakage Current V
IN
= 5.5V
●
±0.1 ±1 µA
I
VFBx
V
FBx
Leakage Current 80 nA
t
SS
Soft-Start Period V
FB
= 7.5% to 92.5% Full Scale 650 875 1200 µs
V
UVLO
Undervoltage Lockout
●
1.9 2.25 V
Individual Regulator Characteristics
Regulator SW300 – 300mA
I
PK
Peak Switch Current Limit V
FB
< V
FBREG
, Duty Cycle < 35% 400 600 800 mA
I
S300
Input DC Bias Current–Reg SW300 Only
Burst Mode Operation (Sleep)
V
FB
= 0.9V, I
LOAD
= 0A, 2.25MHz 32 µA
R
PFET
R
DS(ON)
of P-Channel FET (Note 7) I
SW
= 100mA 0.55
Ω
R
NFET
R
DS(ON)
of N-Channel FET (Note 7) I
SW
= –100mA 0.50
Ω
Regulator SW200A – 200mA
I
PK
Peak Switch Current Limit V
FB
< V
FBREG
, Duty Cycle < 35% 300 400 500 mA
I
S200
Input DC Bias Current–Reg SW200A Only
Burst Mode Operation (Sleep)
V
FB
= 0.9V, I
LOAD
= 0A, 2.25MHz 32 µA
R
PFET
R
DS(ON)
of P-Channel FET (Note 7) I
SW
= 100mA 0.65
Ω
R
NFET
R
DS(ON)
of N-Channel FET (Note 7) I
SW
= –100mA 0.60
Ω
Regulator SW200B – 200mA
I
PK
Peak Switch Current Limit V
FB
< V
FBREG
, Duty Cycle < 35% 300 400 500 mA
I
S200
Input DC Bias Current–Reg SW200B Only
Burst Mode Operation (Sleep)
V
FB
= 0.9V, I
LOAD
= 0A, 2.25MHz 32 µA
R
PFET
R
DS(ON)
of P-Channel FET (Note 7) I
SW
= 100mA 0.65
Ω
R
NFET
R
DS(ON)
of N-Channel FET (Note 7) I
SW
= –100mA 0.60
Ω
Regulator SW100 – 100mA
I
PK
Peak Switch Current Limit V
FB
< V
FBREG
, Duty Cycle < 35% 200 300 400 mA
I
S100
Input DC Bias Current–Reg SW100B Only
Burst Mode Operation (Sleep)
V
FB
= 0.9V, I
LOAD
= 0A, 2.25MHz 32 µA
R
PFET
R
DS(ON)
of P-Channel FET (Note 7) I
SW
= 100mA 0.80
Ω
R
NFET
R
DS(ON)
of N-Channel FET (Note 7) I
SW
= –100mA 0.75
Ω
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3544E is guaranteed to meet performance specifi cations
from 0°C to 85°C. Specifi cations over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.