Datasheet

LTC3544B
3
3544bfb
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3544BE is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: T
J
is calculated from the ambient temperature T
A
and power
dissipation P
D
according to the following formula:
T
J
= T
A
+ (P
D
)(68°C/W).
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
RUN(HIGH)
RUNx Input High Voltage
l
1.0 V
V
RUN(LOW)
RUNx Input Low Voltage
l
0.3 V
I
LSW
SWx Leakage V
RUN
= 0V, V
SW
= 0V or 5.5V, V
IN
= 5.5V ±0.1 ±1 µA
I
RUN
RUN Leakage Current V
IN
= 5.5V
l
±0.1 ±1 µA
I
VFB
V
FBx
Leakage Current 80 nA
t
SS
Soft-Start Period V
FB
= 7.5% to 92.5% Full Scale 650 875 1200 µs
V
UVLO
Undervoltage Lockout
l
1.9 2.25 V
Individual Regulator Characteristics
Regulator SW300 – 300mA
I
PK
Peak Switch Current Limit V
FB
< V
FBREG
, Duty Cycle < 35% 400 600 800 mA
I
S300
Input DC Bias Current–Reg SW300 Only
Active Mode (Pulse Skip)
V
FB
= 0.7V, I
LOAD
= 0A, 2.25MHz 320 µA
R
PFET
R
DS(ON)
of P-Channel FET (Note 7) I
SW
= 100mA 0.55
Ω
R
NFET
R
DS(ON)
of N-Channel FET (Note 7) I
SW
= –100mA 0.50
Ω
Regulator SW200A – 200mA
I
PK
Peak Switch Current Limit V
FB
< V
FBREG
, Duty Cycle < 35% 300 400 500 mA
I
S200
Input DC Bias Current–Reg SW200A Only
Active Mode (Pulse Skip)
V
FB
= 0.7V, I
LOAD
= 0A, 2.25MHz 320 µA
R
PFET
R
DS(ON)
of P-Channel FET (Note 7) I
SW
= 100mA 0.65
Ω
R
NFET
R
DS(ON)
of N-Channel FET (Note 7) I
SW
= –100mA 0.60
Ω
Regulator SW200B – 200mA
I
PK
Peak Switch Current Limit V
FB
< V
FBREG
, Duty Cycle < 35% 300 400 500 mA
I
S200
Input DC Bias Current–Reg SW200B Only
Active Mode (Pulse Skip)
V
FB
= 0.7V, I
LOAD
= 0A, 2.25MHz 320 µA
R
PFET
R
DS(ON)
of P-Channel FET (Note 7) I
SW
= 100mA 0.65
Ω
R
NFET
R
DS(ON)
of N-Channel FET (Note 7) I
SW
= –100mA 0.60
Ω
Regulator SW100 – 100mA
I
PK
Peak Switch Current Limit V
FB
< V
FBREG
, Duty Cycle < 35% 200 300 400 mA
I
S100
Input DC Bias Current–Reg SW100B Only
Active Mode (Pulse Skip)
V
FB
= 0.7V, I
LOAD
= 0A, 2.25MHz 320 µA
R
PFET
R
DS(ON)
of P-Channel FET (Note 7) I
SW
= 100mA 0.80
Ω
R
NFET
R
DS(ON)
of N-Channel FET (Note 7) I
SW
= –100mA 0.75
Ω
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
IN
= 3.6V unless otherwise noted.
Note 4: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 5: The LTC3544B is tested in a proprietary test mode that connects
V
FB
to the output of the error amplifier.
Note 6: Load regulation is inferred by measuring the regulation loop gain.
Note 7: The QFN switch on-resistance is guaranteed by correlation to
wafer level measurements.
Note 8: Guaranteed by long-term current density limitations.