Datasheet

LTC3544B
12
3544bfb
proportional to frequency. Both the DC bias and gate charge
losses are proportional to PV
IN
and thus their effects will
be more pronounced at higher supply voltages.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
, and external inductor R
L
. In con-
tinuous mode, the average output current flowing through
inductor L is “chopped” between the main switch and the
synchronous switch. Thus, the series resistance looking
into the SW pin is a function of both top and bottom
MOSFET R
DS(ON)
and the duty cycle (DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteristics
curves. Thus, to obtain I
2
R losses, simply add R
SW
to
R
L
and multiply the result by the square of the average
output current.
Other losses when in switching operation, including C
IN
and C
OUT
ESR dissipative losses and inductor core losses,
generally account for less than 2% total additional loss.
Thermal Considerations
The LTC3544B requires the package backplane metal to be
well soldered to the PC board. This gives the QFN package
exceptional thermal properties, making it difficult in normal
operation to exceed the maximum junction temperature
of the part. In most applications the LTC3544B does not
dissipate much heat due to its high efficiency. In applica-
tions where the LTC3544B is running at high ambient
temperature with low supply voltage and high duty cycles,
such as in dropout, the heat dissipated may exceed the
maximum junction temperature of the part if it is not well
thermally grounded. If the junction temperature reaches
approximately 150°C, the power switches will be turned
off and the SW nodes will become high impedance.
To avoid the LTC3544B from exceeding the maximum junc-
tion temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
T
R
= P
D
• θ
JA
where P
D
is the power dissipated by the regulator and θ
JA
is the thermal resistance from the junction of the die to
the ambient temperature.
The junction temperature, T
J
, is given by:
T
J
= T
A
+ T
R
where T
A
is the ambient temperature.
As an example, consider the LTC3544B in dropout at an
input voltage of 2.5V, a total load current (all four regula-
tors) of 800mA and an ambient temperature of 85°C. From
the Typical Performance graphs of switch resistance, the
R
DS(ON)
of the 300mA P-channel switch at 85°C can be
estimated as 0.67Ω. Therefore, power dissipated by the
300mA channel is:
P
D
= I
LOAD
2
• R
DS(ON)
= 60mW
Similar analysis on the other channels gives a total power
dissipation of 138mW. For the 3mm × 3mm QFN package,
the θ
JA
is 68°C/W. Thus, the junction temperature of the
regulator is:
T
J
= 85°C + (0.138)(68) = 94.4°C
which is well below the maximum junction temperature
of 125°C.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance R
DS(ON)
.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to (ΔI
LOAD
• ESR), where ESR is the effective series
resistance of C
OUT
. ΔI
LOAD
also begins to charge or dis-
charge C
OUT
, which generates a feedback error signal. The
regulator loop then acts to return V
OUT
to its steady-state
value. During this recovery time V
OUT
can be monitored
for overshoot or ringing that would indicate a stability
problem. For a detailed explanation of switching control
loop theory, see Application Note 76.
applicaTions inForMaTion