Datasheet

LTC3538
12
3538fb
Closing the Feedback Loop
The LTC3538 incorporates voltage mode PWM control.
The control to output gain varies with operation region
(buck, boost, buck-boost), but is usually no greater than
15. The output fi lter exhibits a double pole response, as
given by:
ƒ
FILTER_POLE
=
1
2• π • L •C
OUT
Hz
(in buck mode)
ƒ
FILTER_POLE
=
V
IN
2• V
OUT
• π • L•C
OUT
Hz
(in boost mode)
where L is in Henries and C
OUT
is in Farads.
The output fi lter zero is given by:
ƒ
FILTER_ ZERO
=
1
2• π •R
ESR
•C
OUT
Hz
where R
ESR
is the equivalent series resistance of the
output capacitor.
A troublesome feature in boost mode is the right-half plane
zero (RHP), given by:
ƒ
RHPZ
=
V
IN
2
2• π •I
OUT
•L • V
OUT
Hz
The loop gain is typically rolled off before the RHP zero
frequency.
A simple Type I compensation network can be incorporated
to stabilize the loop, but at a cost of reduced bandwidth and
slower transient response. To ensure proper phase margin
using Type I compensation, the loop must be crossed
over a decade before the LC double pole. Referring to
Figure 4, the unity-gain frequency of the error amplifi er
with the Type I compensation is given by:
ƒ
UG
=
1
2• π •R1•C
P1
Hz
1V
FB
C
P1
V
C
R2
3538 F04
–
+
1
2
V
OUT
R1
Figure 4. Error Amplifi er with Type I Compensation
VIA TO GND PLANE
8
V
IN
7
SW1
6
SW2
5
V
OUT
1
FB
2
V
C
3
GND
4
BURST
V
OUT
3538 F03
Figure 3. LTC3538 Recommended PCB Layout
OPERATION