Datasheet

LTC3536
8
3536fa
block DiagraM
1.75V
–
+
–
+
PWM
AND
OUTPUT
PHASING
GATE
DRIVERS
AND
ANTICROSS
CONDUCTION
L
PEAK
CURRENT
LIMIT
3.4A
UVLO
OSC
Burst Mode
CONTROL
RUN LOGIC
SYNC
SLEEP
SGND
SWB SWC
REVERSE
CURRENT
LIMIT
CURRENT
LIMIT
ERROR
AMP
SW1 SW2
SWD
V
OUT
1.8V TO 5.5V
V
IN
1.8V TO 5.5V
PGND
–0.4A
SWA
–
+
–
+
2.5A
SOFT-START
0.6V
FB
R
TOP
R
BOT
3635 BD
R
T
1 = ON
0 = OFF
C
OUT
–
+
+
RT
MODE/SYNC
1 = BURST
0 = PWM
VC
C
FB
SHDN
C
IN
+