Datasheet
LTC3536
3
3536fa
elecTrical characTerisTics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3536 is tested under pulsed load conditions such that
T
J
≈
T
A
. The LTC3536E is guaranteed to meet specifications
from 0°C to 125°C junction temperature. Specifications over the
–40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LTC3536I is guaranteed over the full –40°C to 125°C operating
junction temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors. The junction temperature
(T
J
, in °C) is calculated from the ambient temperature (T
A
, in °C) and
power dissipation (P
D
, in watts) according to the formula:
T
J
= T
A
+ (P
D
• θ
JA
),
where θ
JA
(in °C/W) is the package thermal impedance.
The l denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at T
A
= 25°C (Note 2). V
IN
= 3.3V, V
OUT
= 3.3V, R
T
= 100kΩ unless otherwise noted.
Note 3: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 4: Current measurements are performed when the LTC3536 is
not switching. The current limit values measured in operation will be
somewhat higher due to the propagation delay of the comparators.
Note 5: Guaranteed by design characterization and correlation with
statistical process controls.
Note 6: Guaranteed by correlation and design.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Quiescent Current, Active (I
VIN
) V
FB
= 0.7V, V
MODE/SYNC
= 0V 800 µA
Input Current Limit V
MODE/SYNC
= 0V (Note 4)
l
2 2.5 A
Peak Current Limit V
MODE/SYNC
= 0V (Note 4) 3.4 4 A
Burst Mode Peak Current Limit V
MODE/SYNC
= V
IN
(Note 4) 0.4 0.6 A
Reverse Current Limit (Note 4)
l
0.3 0.55 A
NMOS Switch Leakage Switch B, C: SW1 = SW2 = 5.5V, V
IN
= 5.5V, V
OUT
= 5.5V 0.1 1 µA
PMOS Switch Leakage Switch A, D: SW1 = SW2 = 0V, V
IN
= 5.5V, V
OUT
= 5.5V 0.1 1 µA
NMOS Switch On-Resistance Switch B (From SW1 to GND) (Note 6)
Switch C (From SW2 to GND) (Note 6)
0.11
0.1
Ω
Ω
PMOS Switch On-Resistance Switch A (From V
IN
to SW1) (Note 6)
Switch D (From V
OUT
to SW2) (Note 6)
0.12
0.145
Ω
Ω
Frequency Accuracy R
T
= 100k
l
0.8 1 1.2 MHz
Frequency Accuracy Default R
T
= V
IN
l
0.96 1.2 1.44 MHz
Internal Soft-Start Time V
FB
from 0.06V to 0.54V 0.6 0.9 1.2 ms
Maximum Duty Cycle Percentage of Period SW2 is Low in Boost Mode
l
88 91 %
Minimum Duty Cycle Percentage of Period SW1 is High in Buck Mode
l
0 %
Error Amplifier AVOL 90 dB
Error Amplifier Sink Current FB = 1.3V, VC = 1V 250 300 µA
Error Amplifier Source Current FB = 0.3V, VC = 0V 400 480 µA
MODE/SYNC Input Logic Threshold Disable Burst Mode Operation 0.3 1 V
MODE/SYNC External Synchronization SYNC Level High
SYNC Level Low
l
l
1.2
0.4
V
V
MODE/SYNC Synchronization Frequency
l
0.3 2 MHz
MODE/SYNC Input Current V
MODE/SYNC
= 5.5V = V
IN
1 µA
SHDN Input Logic Threshold
l
0.3 1 V
SHDN Input Current V
SHDN
= 5.5V = V
IN
1 µA