Datasheet

LTC3536
17
3536fa
Figure 5. Buck-Boost Converter Bode Plot
Figure 6. Error Amplifier with Type I Compensation
Figure 7. Error Amplifier with Type III Compensation
Finally, the magnitude of the quality factor of the power
stage in buck-boost mode operation is given by the fol-
lowing expression:
Q =
LC
OUT
R
LOAD
+R
C
( )
R
S
+R
LOAD
• ε
2
L +C
OUT
R
LOAD
R
C
• ε
2
+R
S
C
OUT
R
LOAD
+R
C
( )
Compensation of the Voltage Loop
The small-signal models of the LTC3536 reveal that the
transfer function from the error amplifier output, VC, to
the output voltage is characterized by a set of resonant
poles and a possible zero generated by the ESR of the
output capacitor as shown in the Bode plot of Figure 5.
In boost mode operation, there is an additional right-half
plane zero that produces phase lag and increasing gain at
higher frequencies. Typically, the compensation network
is designed to ensure that the loop crossover frequency
is low enough that the phase loss from the right-half
plane zero is minimized. The low frequency gain in buck
mode is a constant, but varies with both V
IN
and V
OUT
in
boost mode.
low enough that the resultant crossover frequency of the
control loop is well below the resonant frequency.
In most applications, the low bandwidth of the Type I com-
pensated loop will not provide sufficient transient response
performance. To obtain a wider bandwidth feedback loop,
optimize the transient response, and minimize the size of
the output capacitor, a Type III compensation network as
shown in Figure 7 is required.
applicaTions inForMaTion
–40dB/DEC
–20dB/DEC
BUCK MODE
BOOST MODE
f
RHPZ
3536 F05
f
O
f
PHASE
–270°
–180°
–90°
0°
GAIN
For charging or other applications that do not require an
optimized output voltage transient response, a simple
TypeI compensation network as shown in Figure 6 can
be used to stabilize the voltage loop. To ensure sufficient
phase margin, the gain of the error amplifier must be
+
–
0.6V
FB
GND
3536 F06
LTC3536
C1
V
OUT
R
TOP
R
BOT
VC
+
–
0.6V
FB
GND
3536 F07
LTC3536
R
FB
C
FB
C
POLE
C
FF
R
FF
V
OUT
R
TOP
R
BOT
VC
A Bode plot of the typical Type III compensation network
is shown in Figure 8. The Type III compensation network
provides a pole near the origin which produces a very high
loop gain at DC to minimize any steady-state error in the
regulation voltage. Two zeros located at f
ZERO1
and f
ZERO2
provide sufficient phase boost to allow the loop crossover
frequency to be set above the resonant frequency, f
O
, of
the power stage. The Type III compensation network also
introduces a second and third pole. The second pole, at
frequency f
POLE2
, reduces the error amplifier gain to a
zero slope to prevent the loop crossover from extending
too high in frequency. The third pole at frequency f
POLE3
provides attenuation of high frequency switching noise.