Datasheet

LTC3533
7
3533f
BLOCK DIAGRAM
–
+
–
+
–
+
–
+
–
+
–
+
PWM
LOGIC
AND
OUTPUT
PHASING
GATE
DRIVERS
AND
ANTI-CROSS
CONDUCTION
GND
UVLO
4.5A
1.6V
OSC
SUPPLY
CURRENT
LIMIT
SW A
SW1
V
IN
1.8V TO 5.5V
SW2
SW D
ERROR
AMP
CLAMP
1.22V
I
SENSE
AMP
REVERSE
CURRENT
LIMIT
SW B
RUN
SLEEP
SW C
V
OUT
FB
RUN/SS R
SS
C
SS
V
C
V
IN
BURST
0 = BURST MODE
1 = FIXED FREQUENCY
R
T
R
T
3533 BD
PWM
COMPARATORS
BURST MODE
OPERATION
CONTROL
–0.5A
+
R1
R2
OPERATION
The LTC3533 provides high effi ciency, low noise power
for a wide variety of handheld electronic devices. The LTC
proprietary topology allows input voltages above, below
or equal to the output voltage by properly phasing the
output switches. The error amplifi er output voltage on V
C
determines the output duty cycle of the switches. Since
V
C
is a fi ltered signal, it provides rejection of frequencies
well below the switching frequency. The low R
DS(ON)
, low
gate charge synchronous switches provide high frequency
pulse width modulation control at high effi ciency. High
effi ciency is achieved at light loads when Burst Mode
operation is entered and the LTC3533’s quiescent current
drops to a low 40µA.
LOW NOISE FIXED FREQUENCY OPERATION
Oscillator
The frequency of operation is programmed by an external
resistor from R
T
to ground, according to the following
equation:
f(kHz) = 33,170/R
T
(k)