Datasheet

LTC3533
14
3533fc
For more information www.linear.com/LTC3533
applications inForMation
Closing the Feedback Loop
The LTC3533 incorporates voltage mode PWM control. The
control to output gain varies with operation region (buck,
boost, buck/boost), but is usually no greater than 15. The
output filter exhibits a double pole response, as given by:
f
FILTER_POLE
=
1
2 π L C
OUT
Hz
(inbuckm ode)
f
FILTER_POLE
=
V
IN
2 V
OUT
π L C
OUT
H
z
(inboostm ode)
where L is in Henries and C
OUT
is in Farads.
The output filter zero is given by:
f
FILTER_ ZERO
=
1
2 π R
ESR
C
OUT
H
z
where R
ESR
is the equivalent series resistance of the
output capacitor.
A troublesome feature in boost mode is the right-half plane
zero (RHP), given by:
f
RHPZ
=
V
IN
2
2 π I
OUT
L V
OUT
Hz
The loop gain is typically rolled off before the RHP zero
frequency.
A simple Type I compensation network can be incorporated
to stabilize the loop, but at a cost of reduced bandwidth
and slower transient response. To ensure proper phase
margin using Type I compensation, the loop must be
crossed over a decade before the LC double pole. Referring
to Figure 5, the unity-gain frequency of the error amplifier
with the Type I compensation is given by:
f
UG
=
1
2 π R1 C
P1
H
z
Most applications demand an improved transient response
to allow a smaller output filter capacitor. To achieve a higher
bandwidth, Type III compensation is required, providing
two zeros to compensate for the double-pole response of
the output filter. Referring to Figure 6, the location of the
poles and zeros are given by:
f
POLE1
=
1
2 π 10e
3
R1 C
P1
Hz
(whichisa very low frequency)
f
ZERO1
=
1
2 π R
Z
C
P1
Hz
f
ZERO2
=
1
2 π R1 C
Z1
Hz
f
POLE2
=
1
2 π R
Z
C
P2
Hz
where resistance is in Ohms and capacitance is in Farads.
1.22V
R1
R2
3533 F05
FB
12
V
C
C
P1
V
OUT
11
+
ERROR
AMP
1.22V
R1
R2
3533 F06
FB
12
V
C
C
P1
C
Z1
R
Z
V
OUT
11
C
P2
+
ERROR
AMP
Figure 5. Error Amplifier with Type I Compensation Figure 6. Error Amplifier with Type III Compensation
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