Datasheet

LTC3530
12
3530fb
where f = switching frequency in MHz. Therefore frequency
selection is a compromise between the optimal effi ciency
and the smallest solution size.
Closing the Feedback Loop
The LTC3530 incorporates voltage mode PWM control.
The control to output gain varies with operation region
(buck, boost, buck/boost), but is usually no greater than
15. The output fi lter exhibits a double pole response, as
given by:
f
FILTER
—
POLE
=
1
2• •L•C
OUT
Hz
(in buck mode)
f
FILTER
—
POLE
=
V
IN
2•V
OUT
•  •L•C
OUT
Hz
(in boost mode)
where L is in henries and C
OUT
is in farads.
The output fi lter zero is given by:
f
FILTER
—
ZERO
=
1
2• •R
ESR
•C
OUT
Hz
where R
ESR
is the equivalent series resistance of the
output capacitor.
A troublesome feature in boost mode is the right-half plane
zero (RHP), given by:
f
RHPZ
=
V
IN
2
2• •I
OUT
•L•V
OUT
Hz
The loop gain is typically rolled off before the RHP zero
frequency.
A simple Type I compensation network can be incorporated
to stabilize the loop, but at a cost of reduced bandwidth
and slower transient response. To ensure proper phase
margin using Type I compensation, the loop must be
crossed over a decade before the LC double pole. The
unity-gain frequency of the error amplifi er with the Type
I compensation is given by:
f
UG
=
1
2• •R1•C
P1
Hz (referring to Figure 4).
Most applications demand an improved transient response
to allow a smaller output fi lter capacitor. To achieve a higher
bandwidth, Type III compensation is required, providing
two zeros to compensate for the double-pole response of
the output fi lter. Referring to Figure 5, the location of the
poles and zeros are given by:
f
POLE1

1
2• • 32,000 •R1• CP1
Hz
(which is extremely close to DC)
f
ZERO1
=
1
2• •R
Z
•C
P1
Hz
f
ZERO2
=
1
2• •R1•C
Z1
Hz
f
POLE2
=
1
2• •R
Z
•C
P2
Hz
where resistance is in ohms and capacitance is in
farads.
1.215V
R1
R2
3530 F03
FB
12
V
C
C
P1
V
OUT
11
–
+
ERROR
AMP
1.215V
R1
R2
3530 F04
FB
12
V
C
C
P1
C
Z1
R
Z
V
OUT
11
C
P2
–
+
ERROR
AMP
Figure 4. Error Amplifi er with Type I Compensation
Figure 5. Error Amplifi er with Type III Compensation
APPLICATIONS INFORMATION