Datasheet

LTC3525-3/
LTC3525-3.3/LTC3525-5
7
3525fb
SHDN (Pin 1): Logic-Controlled Shutdown Input. Con-
nect to a voltage >1V to enable the LTC3525. Connect to
a voltage <0.4V to disable the LTC3525.
GND (Pins 2, 5): Ground.
V
IN
(Pin 3): Input Voltage. The LTC3525 is powered from
V
IN
until V
OUT
exceeds V
IN
. Once V
OUT
is greater than (V
IN
+ 0.2V typical), it is powered from V
OUT
. Place a ceramic
bypass capacitor from V
IN
to GND. A minimum value of
1µF is recommended.
V
OUT
(Pin 4): Output Voltage Sense and the Output of the
Synchronous Rectifier. Connect the output filter capacitor
from V
OUT
to GND, close to the IC. A minimum value of
10µF ceramic is recommended. Use 22µF for reduced
output ripple. The output disconnect feature disconnects
V
OUT
from V
IN
when SHDN is <0.4V.
SW (Pin 6): Switch Pin. Connect an inductor from this
pin to V
IN
. An internal antiringing resistor is connected
across SW and V
IN
after the inductor current has dropped
to zero to minimize EMI.
PIN FUNCTIONS
BLOCK DIAGRAM
–
+
+
–
+
–
36
1
2
4
V
REF
I
PK
COMPARATOR
I
VALLEY
COMPARATOR
SLEEP
COMPARATOR
INTEGRATOR
WAKETSD
I
VAL
V
OUT
V
IN
SHDN
SW
I
PK
ADJUST
GND
5
GND
FB
OFFSET
ADJUST
OFFSET
ADJUST
LOGIC
GATE DRIVERS
AND
ANTI-CROSS
CONDUCTION
WELL
SWITCH
V
BEST
V
REF
UVLO
THERMAL
SHUTDOWN
VB
SHUTDOWN
START-UP
UVLO
SHUTDOWN
SHUTDOWN
V
REF
V
SEL
V
OUT
3525 BD
–
+
–
+