Datasheet

LTC3522
8
3522fa
BLOCK DIAGRAM
+
–
+
–
PGOOD1
V
OUT1
6
12
FB1
SHDN1
FILTER
REVERSE I
LIMIT
FORWARD I
LIMIT
PGOOD2
4
13
0.9V
0.85A
+
–
0.250A
+
–
0A
I
ZERO
BUCK-BOOST
PWM
LOGIC
GATE
DRIVES
GATE
DRIVES
BUCK
PWM
LOGIC
BANDGAP
REFERENCE
AND OT
SHUTDOWN
OSCILLATOR
UVLO
1.00V
SOFT-START
RAMP
+
+
–
SOFT-START
RAMP
7
PWM
2
SHDN2
5
D
V
OUT1
10
SW1B
11
SW1A
8
PV
IN1
*
15
PV
IN2
*
INTERNAL
V
CC
CB
A
PGND2PGND1
PGND1
ZERO CROSSING
14
SW2
FB2
+
–
0A
+
–
+
–
0.4A
I
LIMIT
0.548V
3522 BD
0.594V
g
m
PGND1
3
GND
*PV
IN1
AND PV
IN2
MUST BE CONNECTED TOGETHER IN THE APPLICATION.
9
PGND2
SLOPE
COMPENSATION
+
+
–
1
+
+
–
16
1.00V
0.594V
0.9V
0.548V