Datasheet

LTC3499/LTC3499B
12
3499fc
APPLICATIONS INFORMATION
There is a resultant gain increase with a phase lag which
makes it difficult to compensate the loop. At heavy loads
the right half plane zero can occur at a relatively low
frequency. The loop gain is typically rolled off before the
RHP zero frequency.
The typical error amp compensation is shown in Figure 3,
following the equations for the loop dynamics:
f
POLE1
~
1
2 • π • 10e6 • C
C1
( )
which is extremely close to DC.
f
ZERO1
=
1
2 • π • R
Z
• C
C1
( )
f
POLE2
=
1
2 • π • R
Z
• C
C2
( )
Figure 3: Typical Error Amplifier Compensation
3499 F03
V
OUT
C
C1
R
Z
C
C2
FB
–
+
1.22V
R1
R2
8
ERROR AMPLIFIER
6
7
VC
8