Datasheet

LTC3447
15
3447f
Design Example
As a design example, assume the LTC3447 is used in a
single lithium-ion battery-powered cellular phone applica-
tion. The V
IN
will be operating from a maximum of 4.2V
down to about 2.7V. The normal load current requirement
is a maximum of 500mA at 1.4V, but most of the time it will
be in standby mode, requiring only 200µA at 1V. Effi ciency
at both low and high load currents is important.
To ensure that the ripple currents and voltages do not
exceed desired expectations over the DAC output range,
calculations with maximum V
IN
and minimum V
OUT
should
be used. Note that either increasing the output voltage or
decreasing V
IN
will result in a decrease of ripple current
and voltage. Choosing a maximum ripple current, ΔI
L
, of
280mA, Equation 1 can be used to determine the size of
the inductor that should be used.
L
MHz mA
V
V
V
H=
⎛
⎝
⎜
⎞
⎠
⎟
=µ
1
1 280
14 1
14
42
33
()( )
•. –
.
.
.
A 3.3µH inductor works well for this application. For best
effi ciency choose a 640mA or greater inductor with less
than 0.2Ω series resistance.
C
IN
will require an RMS current of at least 0.25A, approxi-
mately I
LOAD(MAX)
/2, overtemperature (see Equation 2). For
C
OUT
, selecting a 4.7µF capacitor with an ESR of 0.25Ω
yields the following ripple voltage using Equation 3.
∆ΩVA
MHz F
mV mV mV
OUT
=+
⎛
⎝
⎜
⎞
⎠
⎟
=
+=
0 280 0 25
1
81 47
70 7 4 77 4
..
()(.)
..
µ
Note that the majority of the ripple voltage is generated
by the capacitor’s ESR. Most ceramic capacitors will have
a typical ESR of 10mΩ or less. Selecting capacitors with
low ESRs will signifi cantly reduce the ripple voltage.
Effi ciency can be improved by taking advantage of the
LT3447’s Burst Mode operation. When entering the standby
mode, ensure that the burst disable bit is set to 0 when
the output voltage DAC is updated. Likewise, when enter-
ing a heavy current load mode, ensure the burst disable
bit is set to 1 when the output voltage DAC is updated.
Figure 11 shows the advantage of utilizing the Burst Mode
function.
APPLICATIO S I FOR ATIO
WUU
U
PACKAGE DESCRIPTIO
U
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
0.38 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
2.38 ±0.10
(2 SIDES)
15
106
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DD10) DFN 1103
0.25 ± 0.05
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.15 ±0.05
0.50
BSC
0.675 ±0.05
3.50 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD
FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
LOAD CURRENT (mA)
EFFICIENCY (%)
100
90
80
70
60
50
40
30
20
10
0
0.1 10 100 1000
3447 F11
1
STBY
NORMAL
DAC(MAX)
DAC(MAX)
DAC(MIN)
BURST
PSK
DAC(MIN)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
Figure 11. Effi ciency vs Load Current ( V
IN
= 4.2V)