Datasheet
LTC3447
14
3447f
junction temperature of the part. The temperature rise
is given by:
T
R
= θ
JA
• P
D
where P
D
is the power dissipated by the regulator and
θ
JA
is the thermal resistance from the junction of the die
to the temperature.
The junction temperature, T
J
, is given by:
T
J
= T
A
+ T
R
where T
A
is the ambient temperature.
As an example, consider the LTC3447 when using an input
voltage of 3.6V, an ambient temperature of 70°C, and a
buck load current of 500mA. From the typical performance
graph of switch resistance, the R
DS(ON)
of the P-channel
switch at 70°C is approximately 0.45Ω. Therefore, power
dissipated by the part is:
P
D
= I
LOAD
2
• R
DS(ON)
= 112.5mW
For the DFN-10 package, the θ
JA
is 43°C/W. Thus, the
junction temperature of the regulator is:
T
J
= 70°C + (0.1125)(43) = 74.8°C
which is well below the maximum junction temperature of
150°C. Note that at higher supply voltages, the junction
temperature is lower due to reduced switch resistance
(R
DS(ON)
).
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3447. These items are also illustrated graphically
in Figures 9 and 10. Check the following in your layout:
1. The power traces, consisting of the GND trace, the
SW trace, and the V
IN
trace should be kept short, direct
and wide.
2. Does the V
OUT
pin connect directly to the output voltage
reference? Ensure that there is no load current running
from the output voltage and the V
OUT
sense pin.
3. Does the FB pin connect directly to the feedback voltage
reference? Ensure that there is no load current running
from the feedback reference voltage and the FB pin.
4. Does the (+) plate of C
IN
connect to V
IN
as closely as
APPLICATIO S I FOR ATIO
WUU
U
possible? This capacitor provides the AC current to the
internal power MOSFETs.
5. Keep the switching node, SW, away from the sensitive
V
OUT
and FB nodes.
6. Keep the (–) plates of C
IN
and C
OUT
as close as pos-
sible.
Figure 9. LTC3447 Suggested Layout
Figure 10. LTC3447 Layout Diagram
SDA
V
CCD
SCL
RUN
SW
V
OUT
VIA
TO
V
OUT
V
IN
GND
PGOOD
FB
R2
R1
L1
C
OUT
C
IN
C2
GND PLANE
GND PLANE
3447 F09
V
IN
V
IN
R2
R1
C2
V
OUT
3447 F11
SDA
V
CCD
SCL
RUN
SW
V
OUT
GND
FB
L1
PGOOD
V
IN
C
IN
C
OUT