Datasheet

LTC3443
6
3443fa
BLOCK DIAGRA
W
–
+
–
+
–
+
–
+
–
+
–
+
9
10
PWM
LOGIC
AND
OUTPUT
PHASING
GATE
DRIVERS
AND
ANTICROSS
CONDUCTION
Burst Mode
OPERATION
CONTROL
5μs DELAY
GND
UVLO
4A
2.4V
SLEEP
MODE/SYNC
1 = Burst Mode
OPERATION
0 = FIXED FREQUENCY
600kHz
OSC
SYNC
SUPPLY
CURRENT
LIMIT
SW A
SW1
PV
IN
V
IN
V
CC
INTERNAL
SW2
V
IN
2.4V TO 5.5V
SW D
I
SENSE
AMP
ERROR
AMP
1.22V
CLAMP
REVERSE
CURRENT
LIMIT
SW B
3.2A
AVERAGE
CURRENT LIMIT
SW C
PGND
–0.4A
7
2
1
+
4 5
PGND
6
V
OUT
8
FB
12
V
C
11
SHDN/SS
SHUTDOWN
R
SS
V
IN
R2
C
SS
R1
3443 BD
V
OUT
2.4V TO 5.25V
PWM
COMPARATORS
–
+
1
100
g
m
= k
THERMAL
SHUTDOWN
÷2
CLAMP
MODE
UU
U
PI FU CTIO S
MODE/SYNC = Low: Disable Burst Mode operation and
maintain low noise, constant frequency operation .
MODE/SYNC = External CLK : Synchronization of the
internal oscillator and Burst Mode operation disable. A
clock pulse width between 100ns and 2μs and a clock
frequency between 1.38MHz and 2.4MHz (twice the
desired frequency) is required to synchronize the IC.
f
OSC
= f
SYNC
/2
V
OUT
(Pin 8): Output of the Synchronous Rectifier. A filter
capacitor is placed from V
OUT
to GND. A ceramic bypass
capacitor is recommended as close to the V
OUT
and GND
pins as possible.
PV
IN
(Pin 9): Power V
IN
Supply Pin. A 10μF ceramic capaci-
tor is recommended as close to the PV
IN
and PGND pins
as possible
V
IN
(Pin 10): Input Supply Pin. Internal V
CC
for the IC.
V
C
(Pin 11): Error Amp Output. A frequency compensation
network is connected from this pin to the FB pin to
compensate the loop. See the section “Compensating the
Feedback Loop” for guidelines.
FB (Pin 12): Feedback Pin. Connect resistor divider tap
here. The output voltage can be adjusted from 2.4V to
5.25V. The feedback reference voltage is typically 1.22V.